{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:12:07Z","timestamp":1747807927459},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/etsym.2010.5512768","type":"proceedings-article","created":{"date-parts":[[2010,7,23]],"date-time":"2010-07-23T09:52:00Z","timestamp":1279878720000},"page":"132-137","source":"Crossref","is-referenced-by-count":19,"title":["Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes"],"prefix":"10.1109","author":[{"given":"R. Alves","family":"Fonseca","sequence":"first","affiliation":[]},{"given":"L.","family":"Dilillo","sequence":"additional","affiliation":[]},{"given":"A.","family":"Bosio","sequence":"additional","affiliation":[]},{"given":"P.","family":"Girard","sequence":"additional","affiliation":[]},{"given":"S.","family":"Pravossoudovitch","sequence":"additional","affiliation":[]},{"given":"A.","family":"Virazel","sequence":"additional","affiliation":[]},{"given":"N.","family":"Badereddine","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"article-title":"Advanced Test Methods for SRAMs - Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies","year":"2009","author":"bosio","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-005-6146-1"},{"key":"ref10","article-title":"Analysis of a Deceptive Destructive Read Memory Fault Model and Recommended Testing","author":"adams","year":"1996","journal-title":"Proc of IEEE North Atlantic Test Workshop"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2000.893615"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref5","first-page":"411","article-title":"Influence of parasitic capacitance variations on 65nm and 32nm predictive model technology SRAM core-cells","author":"di carlo","year":"2008","journal-title":"Proc of IEEE Asian Test Symposium"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843856"},{"key":"ref7","first-page":"256","article-title":"Defect oriented fault analysis for SRAM","author":"huang","year":"2003","journal-title":"Proc of IEEE Asian Test Symposium"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-005-1169-1"},{"article-title":"Testing Semiconductor Memories, Theory and Practice","year":"1998","author":"van de goor","key":"ref9"},{"year":"2007","key":"ref1","article-title":"International Technology Roadmap for Semiconductors (ITRS)"}],"event":{"name":"2010 15th IEEE European Test Symposium (ETS)","start":{"date-parts":[[2010,5,24]]},"location":"Praha, Czech Republic","end":{"date-parts":[[2010,5,28]]}},"container-title":["2010 15th IEEE European Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5508193\/5512725\/05512768.pdf?arnumber=5512768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T18:29:26Z","timestamp":1489861766000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5512768\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/etsym.2010.5512768","relation":{},"subject":[],"published":{"date-parts":[[2010,5]]}}}