{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T08:25:23Z","timestamp":1725524723694},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/etw.2002.1029636","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T22:14:31Z","timestamp":1056579271000},"page":"31-36","source":"Crossref","is-referenced-by-count":3,"title":["Dependable testing of compactor MISR: an imperceptible problem?"],"prefix":"10.1109","author":[{"given":"A.","family":"Hlawiczka","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Kopec","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.108620"},{"key":"ref11","first-page":"203","article-title":"Design-for-test System-on-a-Chip Designs","author":"rajski","year":"1998","journal-title":"Proc IEEE Work Design and Diagnostics of Electronic Circuits and Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1995.470362"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/12.956088"},{"journal-title":"A Test-Per-Clock Logic BIST with Semi- Deterministic Test Patterns and Zero-Aliasing Compactor","year":"0","author":"novak","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.165391"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1997.600278"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.777814"},{"key":"ref8","first-page":"457","article-title":"Modular-Addition Signature Analysis for BIST","author":"wu","year":"1993","journal-title":"Proc of European Test Conference"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/54.211530"},{"key":"ref2","first-page":"29","article-title":"Low Hardware Overhead Deterministic Logic BIST with Zero-Aliasing Compactor","author":"novak","year":"2001","journal-title":"Proc IEEE Work Design and Diagnostics of Electronic Circuits and Systems"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/82.868460"},{"key":"ref9","first-page":"54","article-title":"Bringing Down More Bariers with Design For Test","author":"maunder","year":"1995","journal-title":"IEEE Spectrum"}],"event":{"name":"The Seventh IEEE European Test Workshop","acronym":"ETW-02","location":"Corfu, Greece"},"container-title":["Proceedings The Seventh IEEE European Test Workshop"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7996\/22118\/01029636.pdf?arnumber=1029636","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T21:26:22Z","timestamp":1489181182000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1029636\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/etw.2002.1029636","relation":{},"subject":[]}}