{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T16:59:37Z","timestamp":1730221177983,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/ewdts.2008.5580135","type":"proceedings-article","created":{"date-parts":[[2010,9,22]],"date-time":"2010-09-22T19:57:51Z","timestamp":1285185471000},"page":"155-158","source":"Crossref","is-referenced-by-count":0,"title":["SoC software components diagnosis technology"],"prefix":"10.1109","author":[{"given":"Svetlana","family":"Chumachenko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wajeb","family":"Gharibi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anna","family":"Hahanova","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aleksey","family":"Sushanov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675602"},{"key":"ref3","first-page":"481","article-title":"Algebra-logical method for SoC embedded memory repair","author":"hahanov","year":"2008","journal-title":"Proceedings of the 15 International Conference «Mixed design of integrated circuits and systems"},{"key":"ref10","first-page":"270","author":"akhter","year":"2006","journal-title":"Multi-core Programming"},{"key":"ref6","first-page":"5","article-title":"What is Infrustructure IP?","author":"yervant","year":"2002","journal-title":"IEEE Design & Test of Computers"},{"key":"ref5","first-page":"145","article-title":"Construction of microprocessor tests. 1. The general model. Data processing check","volume":"11","author":"sharshunov","year":"1985","journal-title":"Automation and telemechanics"},{"key":"ref8","first-page":"354","author":"janick","year":"2001","journal-title":"Writing Testbenches Functional Verification of HDL Models"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.112"},{"key":"ref2","volume":"652","author":"abramovici","year":"1998","journal-title":"Digital System Testing and Testable Design"},{"key":"ref9","first-page":"49","article-title":"Guest Editor's Introduction: Advances in Infrastructure IP","author":"yervant","year":"2003","journal-title":"IEEE Design and Test of Computers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271086"}],"event":{"name":"Test Symposium (EWDTS)","start":{"date-parts":[[2008,10,9]]},"location":"Lviv, Ukraine","end":{"date-parts":[[2008,10,12]]}},"container-title":["Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5570120\/5580134\/05580135.pdf?arnumber=5580135","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T00:34:09Z","timestamp":1489883649000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5580135\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2008.5580135","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}