{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T16:59:39Z","timestamp":1730221179124,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/ewdts.2008.5580146","type":"proceedings-article","created":{"date-parts":[[2010,9,22]],"date-time":"2010-09-22T15:57:51Z","timestamp":1285171071000},"page":"163-167","source":"Crossref","is-referenced-by-count":0,"title":["Testability analysis method for hardware and software based on assertion libraries"],"prefix":"10.1109","author":[{"given":"Maryna","family":"Kaminska","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Prikhodchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Artem","family":"Kubirya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pavel","family":"Mocar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"319","article-title":"Digital Test Generation and Design for Testability","volume":"5","author":"grason","year":"1981","journal-title":"\/\/ Journal Digital Systems"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1979.1600103"},{"key":"ref31","article-title":"Fault Detection Test Generation for Sequential Logic Heuristic Tree Search","author":"rutman","year":"1972","journal-title":"IEEE Computer Repository Paper No R-72–187"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.14"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224279"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.170990"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894313"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223950"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998278"},{"key":"ref14","first-page":"119","article-title":"Verification and Testing of Embedded Cores","author":"hemmady","year":"1997","journal-title":"Proc Design SuperCon On-Chip Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/54.679210"},{"key":"ref16","first-page":"145","article-title":"Postroenie testov microptocessirov. 1. Obschaya model","author":"sharshunov","year":"1985","journal-title":"Proverka obrabotki dannih \/\/Avtomatika I telemehanika"},{"key":"ref17","first-page":"139","article-title":"Postroenie testov microptocessirov. 2. Proverka hraneniya i peredachi dannih \/\/Avtomatika i telemehanika","author":"chipulis","year":"1986"},{"article-title":"Advanced Verification Methodology Cookbook. Version 2.0","year":"2006","author":"glasser","key":"ref18"},{"key":"ref19","first-page":"528","article-title":"Verification Methodology Manual for System Verilog","author":"bergeron","year":"2006"},{"key":"ref28","first-page":"185","article-title":"Formal Verification of Backward Compatibility of Microcode \/\/ Computer Aided Verification","volume":"4","author":"arons","year":"2005"},{"journal-title":"IEEE Standard for a Mixed-Signal Test Bus","first-page":"84","year":"2000","key":"ref4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240642"},{"journal-title":"Standard Test Access Port and Boundary–Scan Architecture","first-page":"208","year":"2001","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICMEL.2004.1314941"},{"key":"ref29","first-page":"60","article-title":"Modifikaciya wyfrovich shem s ispolzovaniem metoda analisa testopigodnosti TADATPG \/\/ Radioelectronica i informatika","author":"kulak","year":"2005"},{"first-page":"139","article-title":"Standard for Boundary–Scan Testing of Advanced Digital Networks","year":"2003","key":"ref5"},{"key":"ref8","first-page":"112","article-title":"Novel control pattern generators for interconnect testing","author":"feng","year":"1999","journal-title":"Proc IEEE Int l Symp Defect and Fault Tolerance in VLSI Systems"},{"key":"ref7","first-page":"774","article-title":"Boundary scan BIST methodology for reconfigurable systems","author":"su","year":"0","journal-title":"\/\/ Proceedings of ITC '98"},{"key":"ref2","first-page":"652","article-title":"Digital systems testing and testable design","author":"abramovici","year":"1998"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1993.398806"},{"first-page":"138","article-title":"Draft Standard Testability Method for Embedded Core-based Integrated Circuits","year":"2005","key":"ref1"},{"journal-title":"OVM Class Reference Version 1 0 1","first-page":"286","year":"2008","key":"ref20"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1146238.1146264"},{"journal-title":"C\/C++ Users Journals advanced Solutions for professional developers","year":"2003","author":"samek","key":"ref21"},{"key":"ref24","article-title":"SystemVerilog Assertions for Dummies","author":"mills","year":"2004","journal-title":"SNUG San Jose"},{"journal-title":"Synthesis of Synchronous Assertions with Guarded Atomic Actions","year":"2005","author":"pellauer","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45061-0_67"},{"key":"ref25","first-page":"211","article-title":"The For Spec Temporal Logic: A new temporal property-specification language","volume":"2280","author":"armoni","year":"2002","journal-title":"Tools and Algorithms for Construction and Analysis of Systems \/\/ Lecture Notes in Computer Science"}],"event":{"name":"Test Symposium (EWDTS)","start":{"date-parts":[[2008,10,9]]},"location":"Lviv, Ukraine","end":{"date-parts":[[2008,10,12]]}},"container-title":["Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5570120\/5580134\/05580146.pdf?arnumber=5580146","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T17:23:02Z","timestamp":1489857782000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5580146\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2008.5580146","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}