{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,24]],"date-time":"2026-06-24T17:05:44Z","timestamp":1782320744663,"version":"3.54.5"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/ewdts.2010.5742085","type":"proceedings-article","created":{"date-parts":[[2011,4,7]],"date-time":"2011-04-07T16:00:27Z","timestamp":1302192027000},"page":"390-394","source":"Crossref","is-referenced-by-count":4,"title":["Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD"],"prefix":"10.1109","author":[{"given":"A.","family":"Barkalov","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"L.","family":"Titarenko","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Chmielewski","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"443","article-title":"Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis","volume":"48","author":"chattopadhyay","year":"2005","journal-title":"A Genetic Algorithm Approach The Computer Journal"},{"key":"ref11","first-page":"128","article-title":"Genetic algorithm based state assignment for power and area optimization","volume":"149","author":"xia","year":"2002","journal-title":"IEEP - Comput Dig T"},{"key":"ref12","first-page":"39","article-title":"Optimization of Moore FSM on CPLD","volume":"2","author":"barkalov","year":"2007","journal-title":"Proceedings of the Sixth International Conference"},{"key":"ref13","first-page":"76","article-title":"Reduction in the number of PAL macrocells for the effective Moore FSM implementation","author":"barkalov","year":"2008","journal-title":"IEEE East-West Design & Test Symposium"},{"key":"ref14","first-page":"750","article-title":"Decrease of hardware amount in logic circuit of Moore FSM","author":"barkalov","year":"2008","journal-title":"Przeglad Telekomunikacyjny- Wiadomosci Telekomunikacyjne"},{"key":"ref15","article-title":"CBEAL. LGSynth'91 benchmarks","year":"0","journal-title":"Collaborative Benchmarking and Experimental Algorithmics Laboratory"},{"key":"ref4","author":"barkalov","year":"2006","journal-title":"Design of control units with programmable logic"},{"key":"ref3","author":"de micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"},{"key":"ref6","article-title":"Design of Digital System Using the Programmable Logic Integrated Circuits","author":"solovjev","year":"2001","journal-title":"Hotline - Telecom"},{"key":"ref5","first-page":"65","article-title":"Principles of Optimization of logical circuit of Moore FSM","author":"barkalov","year":"1998","journal-title":"Cybernetics and System Analysis"},{"key":"ref8","article-title":"Synthesis of Finite State Machines: Logic Optimization","author":"villa","year":"1998"},{"key":"ref7","article-title":"Synthesis of Finite State Machines: Functional Optimization","author":"kam","year":"1998"},{"key":"ref2","author":"kania","year":"2004","journal-title":"Logic Synthesis Oriented on Programmable Logic Devices of the PAL type"},{"key":"ref1","author":"baranov","year":"2008","journal-title":"Logic and System Design of Digital Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.16807"}],"event":{"name":"Test Symposium (EWDTS)","location":"St. Petersburg, Russia","start":{"date-parts":[[2010,9,17]]},"end":{"date-parts":[[2010,9,20]]}},"container-title":["2010 East-West Design &amp; Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5738234\/5742029\/05742085.pdf?arnumber=5742085","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T07:10:48Z","timestamp":1490080248000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5742085\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2010.5742085","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}