{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:00:09Z","timestamp":1730221209691,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/ewdts.2010.5742139","type":"proceedings-article","created":{"date-parts":[[2011,4,7]],"date-time":"2011-04-07T16:00:27Z","timestamp":1302192027000},"page":"21-24","source":"Crossref","is-referenced-by-count":0,"title":["Hardware reduction for FSM - Based control units using PAL technology"],"prefix":"10.1109","author":[{"given":"A.","family":"Barkalov","sequence":"first","affiliation":[]},{"given":"L.","family":"Titarenko","sequence":"additional","affiliation":[]},{"given":"S.","family":"Chmielewski","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Logic Synthesis Oriented on Programmable Logic Devices of the PAL type","year":"2004","author":"kania","key":"ref4"},{"journal-title":"The Design Warrior's Guide to FPGAs","year":"2004","author":"maxfield","key":"ref3"},{"journal-title":"Collaborative Benchmarking and Experimental Algorithmics Laboratory","article-title":"CBEAL. LGSynth '91 benchmarks","year":"0","key":"ref10"},{"key":"ref6","first-page":"128","article-title":"Genetic algorithm based state assignment for power and area optimization","volume":"149","author":"xia","year":"2002","journal-title":"IEEP - Comput Dig T"},{"journal-title":"Synthesis and Optimization of Digital Circuits","year":"1994","author":"de micheli","key":"ref5"},{"key":"ref8","first-page":"376","author":"solovjev","year":"2008","journal-title":"Logic design of digital Systems with programmable logic devices"},{"key":"ref7","first-page":"233","author":"barkalov","year":"2009","journal-title":"Logic Synthesis for FSM - Based Control Units"},{"journal-title":"Design of control units with programmable logic","year":"2006","author":"barkalov","key":"ref2"},{"key":"ref9","first-page":"317","article-title":"Hardware reduction for Moore FSM implemented with CPLD","author":"barkalov","year":"2009","journal-title":"Electronics and Telecommunications Quarterly"},{"journal-title":"Logic and System Design of Digital Systems","year":"2008","author":"baranov","key":"ref1"}],"event":{"name":"Test Symposium (EWDTS)","start":{"date-parts":[[2010,9,17]]},"location":"St. Petersburg, Russia","end":{"date-parts":[[2010,9,20]]}},"container-title":["2010 East-West Design &amp; Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5738234\/5742029\/05742139.pdf?arnumber=5742139","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T06:46:36Z","timestamp":1490078796000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5742139\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2010.5742139","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}