{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:21:08Z","timestamp":1729621268738,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/ewdts.2010.5742153","type":"proceedings-article","created":{"date-parts":[[2011,4,7]],"date-time":"2011-04-07T12:00:27Z","timestamp":1302177627000},"page":"171-174","source":"Crossref","is-referenced-by-count":0,"title":["Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function"],"prefix":"10.1109","author":[{"given":"S.","family":"Ostanin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Muchamedov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"272","DOI":"10.1145\/157485.164890","article-title":"zero-suppressed bdds for set manipulation in combinatorial problems","author":"minato","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref10","first-page":"237","article-title":"Easy Testable Combinational Circuit Design","author":"matrosova","year":"2004","journal-title":"Proc the 6th International Workshop on Boolean Problems (IWBP'04)"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"642","DOI":"10.1145\/157485.165078","article-title":"bdd based decomposition of logic functions with application to fpga synthesis","author":"lai","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref5","article-title":"An Introduction to Zero-Suppressed Binary Decision Diagrams","author":"mishchenko","year":"2001","journal-title":"Technical Report"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"977","DOI":"10.1109\/43.511577","article-title":"OBDD-based function decomposition: Algorithms and implementation","volume":"15","author":"lai","year":"1996","journal-title":"IEEE Trans Computer-Aided Design"},{"key":"ref7","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3154-8_11","article-title":"FPGA Design by Generalized Functional Decomposition","author":"sasao","year":"1993","journal-title":"Logic Synthesis and Optimization"},{"key":"ref2","first-page":"129","article-title":"Easy Testable Combinational Circuit Design","author":"matrosova","year":"1999","journal-title":"Avtomatika i Telemechanika"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.541442"},{"key":"ref1","first-page":"42","article-title":"Full Test Pattern Generation for circuits designed ith to-level factorized synthesis methods","author":"matrosova","year":"1978","journal-title":"Avtomatika i vichislitelnaja technika"}],"event":{"name":"Test Symposium (EWDTS)","start":{"date-parts":[[2010,9,17]]},"location":"St. Petersburg, Russia","end":{"date-parts":[[2010,9,20]]}},"container-title":["2010 East-West Design & Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5738234\/5742029\/05742153.pdf?arnumber=5742153","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T18:11:27Z","timestamp":1497895887000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5742153\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2010.5742153","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}