{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:00:16Z","timestamp":1730221216113,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/ewdts.2011.6116418","type":"proceedings-article","created":{"date-parts":[[2012,1,6]],"date-time":"2012-01-06T14:28:21Z","timestamp":1325860101000},"page":"72-83","source":"Crossref","is-referenced-by-count":0,"title":["Verification and diagnosis of SoC HDL-code"],"prefix":"10.1109","author":[{"given":"Vladimir","family":"Hahanov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Dong Won Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Olesya","family":"Guz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aleksey","family":"Priymak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2007.371239"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378280"},{"key":"18","first-page":"1","article-title":"Hardware design and realization of matrix converter based on DSP & CPLD","author":"hu","year":"2009","journal-title":"3rd International Conference Power Electronics Systems and Applications"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICMEL.2008.4559311"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484725"},{"key":"13","first-page":"1689","author":"marinissen","year":"2010","journal-title":"Testing TSV-based Three-dimensional Stacked ICs \/\/ DATE 2010"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.917412"},{"key":"11","first-page":"6","volume":"26","author":"marinissen","year":"2009","journal-title":"Guest Editors' Introduction The Status of IEEE Std 1500 -IEEE Design & Test of Computers"},{"journal-title":"IEEE Std 1800-2009 IEEE Standard for System Verilog-unified Hardware Design Specification and Verification Language","year":"0","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2008.4580146"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.1982.290951"},{"key":"22","first-page":"413","article-title":"DEV. Design explorer for verification","author":"soon","year":"2009","journal-title":"Integrated Circuits ISIC '09 Proceedings of the 2009 12th International Symposium"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCTD.2009.172"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923092"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/ICIECS.2010.5677734"},{"key":"26","first-page":"448","author":"gorbatov","year":"2006","journal-title":"Discrete Mathematics"},{"key":"3","first-page":"160","author":"bondaryenko","year":"2010","journal-title":"Infrastructure for Brain-like Computing"},{"key":"2","first-page":"320","author":"parchomenko","year":"1981","journal-title":"Technical Diagnosis Basics (Optimization of Diagnosis Algorithms Hardware Tools)"},{"key":"10","first-page":"276","article-title":"The core test wrapper handbook","author":"da silva","year":"2006","journal-title":"Rationale and Application of IEEE Std 1500\""},{"key":"1","first-page":"460","author":"parchomenko","year":"1976","journal-title":"Technical Diagnosis Basics"},{"key":"7","first-page":"242","author":"hahanov","year":"1995","journal-title":"Technical Diagnosis of Digital and Microprocessor Structures Manual"},{"key":"6","first-page":"264","author":"hahanov","year":"2006","journal-title":"VHDL+Verilog = Synthesis in Minutes"},{"key":"5","first-page":"492","author":"semenets","year":"2003","journal-title":"Design of Digital Systems by Using VHDL Language"},{"key":"4","first-page":"528","author":"hahanov","year":"2010","journal-title":"Design and Verification of Digital Systems on Chips"},{"journal-title":"IEEE Standard for Reduced-pin and Enhanced - Functionality Test Access Port and Boundary-scan Architecture IEEE Std 1149 7-2009","first-page":"985","year":"0","key":"9"},{"key":"8","first-page":"436","article-title":"Logic simulating and testing digital devices","author":"skobtsov","year":"2005","journal-title":"Donetsk IPMM NSA of Ukraine DonNTU"}],"event":{"name":"Test Symposium (EWDTS)","start":{"date-parts":[[2011,9,9]]},"location":"Sevastopol, Ukraine","end":{"date-parts":[[2011,9,12]]}},"container-title":["2011 9th East-West Design &amp; Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6107929\/6116407\/06116418.pdf?arnumber=6116418","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T13:38:29Z","timestamp":1490103509000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6116418\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2011.6116418","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}