{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,28]],"date-time":"2025-07-28T21:43:54Z","timestamp":1753739034908},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/ewdts.2011.6116574","type":"proceedings-article","created":{"date-parts":[[2012,1,6]],"date-time":"2012-01-06T19:28:21Z","timestamp":1325878101000},"page":"131-135","source":"Crossref","is-referenced-by-count":1,"title":["Maintaining uniformity in the processes of encryption and decryption with a variable number of encryption rounds"],"prefix":"10.1109","author":[{"given":"L.","family":"Smolinski","sequence":"first","affiliation":[]}],"member":"263","reference":[{"journal-title":"Virtex II pro Architecture and Configuration","year":"2006","author":"tai","key":"13"},{"journal-title":"Xilinx Virtex Devices Variable Input LUT Architecture","year":"2004","author":"krueger","key":"14"},{"journal-title":"Synthesis and Scripting Techniques for Designing Multi Asynchronous Clock Designs","year":"2001","author":"cummings","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1147\/rd.383.0243"},{"journal-title":"Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog","year":"2008","author":"cummings","key":"3"},{"journal-title":"Architektury Akceleratoro?w Kryptograficznych Opartych na Uk?adach Logicznych FPGA","year":"2004","author":"rogawski","key":"2"},{"journal-title":"A compact and efficient fpga implementation of the DES algorithm","year":"2004","author":"saqib","key":"1"},{"journal-title":"Synteza uk?ado?w cyfrowych","year":"2003","author":"?uba","key":"10"},{"journal-title":"Kryptografia","year":"2005","author":"douglas","key":"7"},{"journal-title":"Je?zyk Verilog W Projektowaniu Uk?ado?w FPGA\"","year":"2001","author":"bieganowski","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20030574"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-07324-7"},{"key":"9","article-title":"Projektowanie uk?ado?w cyfrowych Z wykorzystaniem je?zyka VHDL","author":"zwolmski","year":"2007","journal-title":"WKi?"},{"journal-title":"Kryptografia Dla Praktyko?w","year":"2005","author":"schneider","key":"8"}],"event":{"name":"Test Symposium (EWDTS)","start":{"date-parts":[[2011,9,9]]},"location":"Sevastopol, Ukraine","end":{"date-parts":[[2011,9,12]]}},"container-title":["2011 9th East-West Design & Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6107929\/6116407\/06116574.pdf?arnumber=6116574","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T17:38:52Z","timestamp":1490117932000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6116574\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2011.6116574","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}