{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T04:29:31Z","timestamp":1729657771722,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/ewdts.2013.6673108","type":"proceedings-article","created":{"date-parts":[[2013,12,4]],"date-time":"2013-12-04T14:45:40Z","timestamp":1386168340000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["Generating pipeline integrated circuits using C2HDL converter"],"prefix":"10.1109","author":[{"given":"Denis","family":"Dubrov","sequence":"first","affiliation":[]},{"given":"Alexander","family":"Roshal","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"3"},{"key":"2","first-page":"962","article-title":"Automatic estimation of calculation error subject to initial data and rounding errors in parallelizing system","author":"cherdantsev","year":"2006","journal-title":"Proceedings of the Third International Conference Parallel Computations and Control Problems"},{"key":"10","first-page":"526","article-title":"Open parallelizing system 2006","author":"steinberg","year":"2006","journal-title":"Proceedings of the Third International Conference Parallel Computations and Control Problems"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.07.001"},{"year":"0","key":"7"},{"journal-title":"Advanced Compiler Design and Implementation","year":"1997","author":"muchnick","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4471-0249-6"},{"key":"4","first-page":"865","article-title":"An experimental c to hdl converter based on dialog high-level optimizing parallelizer","author":"dubrov","year":"2010","journal-title":"Proceedings of the Fifth International Conference Parallel Computing and Control Problems"},{"key":"9","first-page":"216","article-title":"Dialogue-based optimizing parallelizing tool and c2hdl converter","author":"steinberg","year":"2009","journal-title":"Proceedings of IEEE East-West Design &Test Symposium (EWDTS'09)"},{"key":"8","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/MICRO.1994.717412","article-title":"Iterative modulo scheduling: An algorithm for software pipelining loops","author":"ramakrishna rau","year":"1994","journal-title":"Proceedings of the 27th Annual International Symposium on Microarchitecture"},{"key":"11","first-page":"542","article-title":"Calculation of pipeline start dalays that takes into consideration data send time","author":"steinberg","year":"2006","journal-title":"Proceedings of the Third International Conference Parallel Computations and Control Problems"},{"key":"12","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1145\/193209.193217","article-title":"SUIF: An infrastructure for research on parallelizing and optimizing compilers","volume":"29","author":"wilson","year":"1994","journal-title":"ACM SIGPLAN Notices"}],"event":{"name":"2013 11th East-West Design and Test Symposium (EWDTS)","start":{"date-parts":[[2013,9,27]]},"location":"Rostov-on-Don, Russia","end":{"date-parts":[[2013,9,30]]}},"container-title":["East-West Design &amp; Test Symposium (EWDTS 2013)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6663756\/6673074\/06673108.pdf?arnumber=6673108","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,4]],"date-time":"2019-08-04T08:18:06Z","timestamp":1564906686000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6673108\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2013.6673108","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}