{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T17:30:04Z","timestamp":1725384604845},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/ewdts.2014.7027112","type":"proceedings-article","created":{"date-parts":[[2015,2,5]],"date-time":"2015-02-05T19:24:26Z","timestamp":1423164266000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Method for diagnosing SoC HDL-code"],"prefix":"10.1109","author":[{"given":"Vladimir","family":"Hahanov","sequence":"first","affiliation":[]},{"given":"Sergey","family":"Zaychenko","sequence":"additional","affiliation":[]},{"given":"Valeria","family":"Varchenko","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1260943"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.143"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810303"},{"key":"11","first-page":"73","article-title":"Logic associative computer","author":"hahanov","year":"2011","journal-title":"Electronic Simulation"},{"key":"12","first-page":"299","article-title":"A diagnostic model for detecting functional violation in HDL-code of SoC","author":"umerah","year":"0","journal-title":"Proc of IEEE East-West Design and Test Symposium"},{"journal-title":"Infrastructure for Brain-like Computing","year":"2010","author":"bondarenko","key":"3"},{"journal-title":"Technical Diagnosis Basics (Optimization of Diagnosis Algorithms Hardware Tools)","year":"1981","author":"parhomenko","key":"2"},{"journal-title":"Technical Diagnosis Basics","year":"1976","author":"parhomenko","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.917412"},{"year":"0","key":"7"},{"journal-title":"VHDL+Verilog = Synthesis for Minutes","year":"2006","author":"hahanov","key":"6"},{"journal-title":"Design of Digital Systems by Using VHDL Language","year":"2003","author":"semenets","key":"5"},{"journal-title":"Design and Verification of Digital Systems on Chips","year":"2010","author":"hahanov","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.10"},{"journal-title":"The Core Test Wrapper Handbook Rationale and Application of IEEE Std 1500","year":"0","author":"da silva","key":"8"}],"event":{"name":"2014 East-West Design & Test Symposium (EWDTS)","start":{"date-parts":[[2014,9,26]]},"location":"Kiev, Ukraine","end":{"date-parts":[[2014,9,29]]}},"container-title":["Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7000956\/7027034\/07027112.pdf?arnumber=7027112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T04:29:57Z","timestamp":1490329797000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7027112\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2014.7027112","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}