{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:01:42Z","timestamp":1730221302935,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/ewdts.2015.7493130","type":"proceedings-article","created":{"date-parts":[[2016,6,17]],"date-time":"2016-06-17T00:15:55Z","timestamp":1466122555000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["A fault-tolerant combinational circuit design"],"prefix":"10.1109","author":[{"given":"S.","family":"Ostanin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.","family":"Kirienko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Lavrov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.403723"},{"key":"ref11","first-page":"1","article-title":"Design of Self-Testing Checkers for Unidirectional Error Detecting Codes","volume":"92","author":"piestrak","year":"1995","journal-title":"Scientific Papers of the Inst of Techn Cybern of the Wroclaw Univ of Technology"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2014.7027072"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1993.627361"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2001.966793"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030177"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510852"},{"article-title":"Error Detecting Logic for Digital Computers","year":"1968","author":"sellers","key":"ref5"},{"key":"ref8","first-page":"162","article-title":"Self-Checking Synchronous FSM network Design","author":"matrosova","year":"1998","journal-title":"Proc IEEE Int'l Workshop on I Testing"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/BF00971960"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/12.663771"},{"key":"ref1","first-page":"43","article-title":"Probabilistic logics and the synthesis of reliable from unreliable components","author":"von neumann","year":"1958","journal-title":"Automata Studies"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004589"}],"event":{"name":"2015 IEEE East-West Design & Test Symposium (EWDTS)","start":{"date-parts":[[2015,9,26]]},"location":"Batumi, Georgia","end":{"date-parts":[[2015,9,29]]}},"container-title":["2015 IEEE East-West Design &amp; Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7488713\/7493093\/07493130.pdf?arnumber=7493130","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T21:17:57Z","timestamp":1489785477000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7493130\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2015.7493130","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}