{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T08:58:40Z","timestamp":1767085120633},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/ewdts.2015.7493159","type":"proceedings-article","created":{"date-parts":[[2016,6,17]],"date-time":"2016-06-17T00:15:55Z","timestamp":1466122555000},"page":"1-4","source":"Crossref","is-referenced-by-count":9,"title":["Clock gating and multi-VTH low power design methods based on 32\/28 nm ORCA processor"],"prefix":"10.1109","author":[{"given":"Vazgen","family":"Melikyan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eduard","family":"Babayan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anush","family":"Melikyan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davit","family":"Babayan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Poghos","family":"Petrosyan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edvard","family":"Mkrtchyan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PrimeAsia.2013.6731222"},{"journal-title":"ORCA documentation","year":"2008","key":"ref3"},{"key":"ref6","first-page":"2011","author":"melikyan","year":"0","journal-title":"IC Synthesis and Optimization Challenges and Solutions"},{"key":"ref5","first-page":"15.06","article-title":"Low-power design of digital signal processing block for integrated power meter","author":"jovanovic","year":"2009","journal-title":"LIII KonferenciJa ETRAN"},{"key":"ref2","first-page":"80","article-title":"Low power design of digital ICs (based on SAED 90nm Educational Design Kit)","author":"melikyan","year":"2012","journal-title":"Instructional guidelines for advanced laboratory works"},{"key":"ref1","article-title":"Power optimization approach of ORCA processor for 32128 nm technology node","author":"babayan","year":"0","journal-title":"CSIT-2015 to be published"}],"event":{"name":"2015 IEEE East-West Design & Test Symposium (EWDTS)","start":{"date-parts":[[2015,9,26]]},"location":"Batumi, Georgia","end":{"date-parts":[[2015,9,29]]}},"container-title":["2015 IEEE East-West Design & Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7488713\/7493093\/07493159.pdf?arnumber=7493159","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T16:05:33Z","timestamp":1489766733000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7493159\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2015.7493159","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}