{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T03:55:24Z","timestamp":1725594924642},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/ewdts.2019.8884401","type":"proceedings-article","created":{"date-parts":[[2019,11,5]],"date-time":"2019-11-05T11:34:05Z","timestamp":1572953645000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Advanced Indication of the Self-Timed Circuits"],"prefix":"10.1109","author":[{"given":"Yury","family":"Stepchenkov","sequence":"first","affiliation":[]},{"given":"Yury","family":"Diachenko","sequence":"additional","affiliation":[]},{"given":"Yury","family":"Rogdestvenski","sequence":"additional","affiliation":[]},{"given":"Yury","family":"Shikunov","sequence":"additional","affiliation":[]},{"given":"Denis","family":"Diachenko","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2008.4610935"},{"journal-title":"Theory of the logic design Course slides","year":"0","author":"marakhovsky","key":"ref3"},{"journal-title":"H-trigger","year":"2009","author":"stepchenkov","key":"ref5"},{"key":"ref2","first-page":"368","author":"kishinevsky","year":"1994","journal-title":"Concurrent Hardware The Theory and Practice of Self-Timed Design"},{"journal-title":"Functional cell library for designing self-timed semi-custom chips on gate arrays 5503\/5507","year":"2017","author":"stepchenkov","key":"ref1"}],"event":{"name":"2019 IEEE East-West Design & Test Symposium (EWDTS)","start":{"date-parts":[[2019,9,13]]},"location":"Batumi, Georgia","end":{"date-parts":[[2019,9,16]]}},"container-title":["2019 IEEE East-West Design &amp; Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8871308\/8884369\/08884401.pdf?arnumber=8884401","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:45:37Z","timestamp":1658155537000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8884401\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/ewdts.2019.8884401","relation":{},"subject":[],"published":{"date-parts":[[2019,9]]}}}