{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:53:14Z","timestamp":1765356794513},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/ewdts50664.2020.9225029","type":"proceedings-article","created":{"date-parts":[[2020,10,15]],"date-time":"2020-10-15T16:00:47Z","timestamp":1602777647000},"page":"1-8","source":"Crossref","is-referenced-by-count":11,"title":["FPGA Implementation of a Low Latency and High SFDR Direct Digital Synthesizer for Resource-Efficient Quantum-Enhanced Communication"],"prefix":"10.1109","author":[{"given":"N. Fajar R.","family":"Annafianto","sequence":"first","affiliation":[]},{"given":"M.V.","family":"Jabir","sequence":"additional","affiliation":[]},{"given":"I.A.","family":"Burenkov","sequence":"additional","affiliation":[]},{"given":"H.F.","family":"Ugurdag","sequence":"additional","affiliation":[]},{"given":"A.","family":"Battou","sequence":"additional","affiliation":[]},{"given":"S.V.","family":"Polyakov","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SIPROCESS.2019.8868732"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"243","DOI":"10.1109\/IWSDA.2007.4408368","article-title":"An Area Optimized Direct Digital Frequency Synthesizer Based on Improved Hybrid CORDIC Algorithm","author":"xin","year":"2007","journal-title":"Proceedings of the Fifth International Workshop on Signal Design and Its Applications in Communications"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1364\/OPTICA.5.000227"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2019.8920330"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECDS.2017.8389648"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2005.856908"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351174"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCNT.2013.6726502"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2483422"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1364\/CLEO_QELS.2020.FF1D.1"}],"event":{"name":"2020 IEEE East-West Design & Test Symposium (EWDTS)","start":{"date-parts":[[2020,9,4]]},"location":"Varna, Bulgaria","end":{"date-parts":[[2020,9,7]]}},"container-title":["2020 IEEE East-West Design &amp; Test Symposium (EWDTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9220087\/9224633\/09225029.pdf?arnumber=9225029","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T11:34:30Z","timestamp":1656329670000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9225029\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ewdts50664.2020.9225029","relation":{},"subject":[],"published":{"date-parts":[[2020,9]]}}}