{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T14:08:53Z","timestamp":1725458933277},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/ewme.2016.7496466","type":"proceedings-article","created":{"date-parts":[[2016,6,25]],"date-time":"2016-06-25T11:38:59Z","timestamp":1466854739000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["A tool set for teaching design-for-testability of digital circuits"],"prefix":"10.1109","author":[{"given":"S.","family":"Kostin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Orasson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Ubar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"journal-title":"Department of Computer Engineering","year":"2012","key":"ref3"},{"year":"0","key":"ref10"},{"journal-title":"Combinational Gate-Level Versions","year":"2012","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/BEC.2014.7320567"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510828"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456929"},{"year":"0","key":"ref7"},{"key":"ref2","first-page":"785","article-title":"A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran","author":"brglez","year":"1985","journal-title":"Proc of the International Test Conference"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EAEEIE.2008.4610171"},{"key":"ref1","article-title":"VLSI Test Principles and Architectures. Design for Testability","author":"wang","year":"2006","journal-title":"Elsevier"}],"event":{"name":"2016 11th European Workshop on Microelectronics Education (EWME)","start":{"date-parts":[[2016,5,11]]},"location":"Southampton, United Kingdom","end":{"date-parts":[[2016,5,13]]}},"container-title":["2016 11th European Workshop on Microelectronics Education (EWME)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7492696\/7496453\/07496466.pdf?arnumber=7496466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T22:55:39Z","timestamp":1475189739000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7496466\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/ewme.2016.7496466","relation":{},"subject":[],"published":{"date-parts":[[2016,5]]}}}