{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,18]],"date-time":"2025-10-18T23:07:30Z","timestamp":1760828850786},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,9]]},"DOI":"10.1109\/fdl.2008.4641449","type":"proceedings-article","created":{"date-parts":[[2008,10,14]],"date-time":"2008-10-14T15:14:34Z","timestamp":1223997274000},"page":"221-226","source":"Crossref","is-referenced-by-count":8,"title":["Using SystemC for an extended MATLAB\/Simulink verification flow"],"prefix":"10.1109","author":[{"given":"Kai","family":"Hylla","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan-Hendrik","family":"Oetjens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wolfgang","family":"Nebel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","journal-title":"Simulink Design Verifier","key":"3"},{"year":"0","journal-title":"Open Verification Methodology","key":"2"},{"key":"10","article-title":"using matlab and simulink in a systemc verification environment","author":"boland","year":"2005","journal-title":"Proceedings of Design and Verification Conference DVCon"},{"year":"0","journal-title":"Advanced Verification Methodology","key":"1"},{"year":"0","journal-title":"SystemC Library","key":"7"},{"year":"0","journal-title":"Simulink Verification and Validation http","key":"6"},{"year":"0","journal-title":"Simulink Real-Time Workshop","key":"5"},{"year":"0","journal-title":"Simulink Fixed Point","key":"4"},{"year":"0","journal-title":"Verification Methodology Manual for SystemVerilog","key":"9"},{"year":"0","journal-title":"Universal Reuse Methodology","key":"8"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/DATE.2007.364675"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1145\/307418.307596"}],"event":{"name":"Design Languages (FDL)","start":{"date-parts":[[2008,9,23]]},"location":"Stuttgart","end":{"date-parts":[[2008,9,25]]}},"container-title":["2008 Forum on Specification, Verification and Design Languages"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4636106\/4641405\/04641449.pdf?arnumber=4641449","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T16:14:43Z","timestamp":1489680883000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4641449\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,9]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/fdl.2008.4641449","relation":{},"subject":[],"published":{"date-parts":[[2008,9]]}}}