{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,29]],"date-time":"2026-01-29T22:32:43Z","timestamp":1769725963071,"version":"3.49.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,9,15]],"date-time":"2020-09-15T00:00:00Z","timestamp":1600128000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,15]],"date-time":"2020-09-15T00:00:00Z","timestamp":1600128000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,15]],"date-time":"2020-09-15T00:00:00Z","timestamp":1600128000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002347","name":"Federal Ministry of Education and Research (BMBF)","doi-asserted-by":"publisher","award":["16ME0127,16ME0135"],"award-info":[{"award-number":["16ME0127,16ME0135"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002347","name":"BMBF project VerSys","doi-asserted-by":"publisher","award":["01IW19001"],"award-info":[{"award-number":["01IW19001"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001659","name":"German Research Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,9,15]]},"DOI":"10.1109\/fdl50818.2020.9232941","type":"proceedings-article","created":{"date-parts":[[2020,11,3]],"date-time":"2020-11-03T21:18:39Z","timestamp":1604438319000},"page":"1-7","source":"Crossref","is-referenced-by-count":23,"title":["Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study"],"prefix":"10.1109","author":[{"given":"Vladimir","family":"Herdt","sequence":"first","affiliation":[]},{"given":"Daniel","family":"Grosse","sequence":"additional","affiliation":[]},{"given":"Eyck","family":"Jentzsch","sequence":"additional","affiliation":[]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","year":"0","journal-title":"RISC-V Torture Test Generator"},{"key":"ref11","article-title":"Towards specification and testing of RISC- VISA compliance","author":"herdt","year":"2020","journal-title":"DATE"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714912"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218629"},{"key":"ref14","year":"0","journal-title":"riscv-dv"},{"key":"ref15","year":"0","journal-title":"RISC-V formal verification framework"},{"key":"ref16","year":"0","journal-title":"OneSpin 360 DV RISC-V Verification App"},{"key":"ref17","year":"0","journal-title":"Formal specification of RISC- VISA in kami"},{"key":"ref18","year":"0","journal-title":"Riscv sail model"},{"key":"ref19","year":"2011","journal-title":"IEEE Standard SystemC Language Reference Manual"},{"key":"ref4","article-title":"Mi-croTESK: specification-based tool for constructing test program generators","author":"chupilko","year":"2017","journal-title":"HVC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176425"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19583-9_13"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775907"},{"key":"ref8","year":"0","journal-title":"RISC- VISA tests"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1572272.1572303"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-10702-8_13"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1277900"},{"key":"ref9","year":"0","journal-title":"RISC- V compliance task group"},{"key":"ref20","author":"grobe","year":"2010","journal-title":"Quality-Driven SystemC Design"},{"key":"ref22","volume":"ii","year":"2019","journal-title":"The RISC-V Instruction Set Manual"},{"key":"ref21","volume":"i","author":"waterman","year":"2019","journal-title":"The RISC-V Instruction Set Manual"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2020.101756"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2018.8524047"}],"event":{"name":"2020 Forum for Specification and Design Languages (FDL)","location":"Kiel, Germany","start":{"date-parts":[[2020,9,15]]},"end":{"date-parts":[[2020,9,17]]}},"container-title":["2020 Forum for Specification and Design Languages (FDL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9226655\/9232930\/09232941.pdf?arnumber=9232941","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:44:33Z","timestamp":1656344673000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9232941\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9,15]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/fdl50818.2020.9232941","relation":{},"subject":[],"published":{"date-parts":[[2020,9,15]]}}}