{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T20:19:15Z","timestamp":1772569155451,"version":"3.50.1"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T00:00:00Z","timestamp":1694563200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T00:00:00Z","timestamp":1694563200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,13]]},"DOI":"10.1109\/fdl59689.2023.10272195","type":"proceedings-article","created":{"date-parts":[[2023,10,9]],"date-time":"2023-10-09T14:23:26Z","timestamp":1696861406000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Instruction-Level Modeling and Evaluation of a Cache-Less Grid of Processing Cells"],"prefix":"10.1109","author":[{"given":"Vivek","family":"Govindasamy","sequence":"first","affiliation":[{"name":"CECS, University of California, Irvine,Irvine,California,USA"}]},{"given":"Rainer","family":"D\u00f6mer","sequence":"additional","affiliation":[{"name":"CECS, University of California, Irvine,Irvine,California,USA"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"crossref","first-page":"557","DOI":"10.1145\/1854273.1854350","article-title":"A case for NUMA-aware contention management on multicore systems","author":"blagodurov","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3607548"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/92.678891"},{"key":"ref23","first-page":"1","year":"2012","journal-title":"IEEE Standard for Standard SystemC Language Reference Manual"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-00515-3"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1006\/cviu.1997.0587"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01764-3"},{"key":"ref22","author":"gr\u00f6tker","year":"2007","journal-title":"System Design with SystemC"},{"key":"ref10","article-title":"Computer organization and design ARM edition: the hardware software interface","author":"patterson","year":"2016","journal-title":"Morgan Kaufmann"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2026356"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977115"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref16","article-title":"Epiphany-v: A 1024 processor 64-bit risc system-on-chip","author":"olofsson","year":"2016","journal-title":"ArXiv Preprint"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.1986.4767851"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2018.8524047"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"613","DOI":"10.1145\/359576.359579","article-title":"Can programming be liberated from the von Neumann style? A functional style and its algebra of programs","volume":"21","author":"backus","year":"0","journal-title":"Communications of the ACM"},{"key":"ref7","author":"stallings","year":"2003","journal-title":"Computer Organization and Architecture Designing for Performance"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/40.888703"},{"key":"ref4","article-title":"Minimizing Memory Contention in an APNG Encoder using a Grid of Processing Cells","author":"govindasamy","year":"2022","journal-title":"IESS"},{"key":"ref3","author":"d\u00f6mer","year":"2022","journal-title":"A Grid of Processing Cells (GPC) with Local Memories"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/85.238389"},{"key":"ref5","article-title":"Demonstrating Scalability of the Checkerboard GPC with SystemC TLM-2.0","author":"wang","year":"2022","journal-title":"IESS"}],"event":{"name":"2023 Forum on Specification & Design Languages (FDL)","location":"Turin, Italy","start":{"date-parts":[[2023,9,13]]},"end":{"date-parts":[[2023,9,15]]}},"container-title":["2023 Forum on Specification & Design Languages (FDL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10272030\/10272044\/10272195.pdf?arnumber=10272195","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,30]],"date-time":"2023-10-30T14:38:29Z","timestamp":1698676709000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10272195\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,13]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/fdl59689.2023.10272195","relation":{},"subject":[],"published":{"date-parts":[[2023,9,13]]}}}