{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,24]],"date-time":"2025-06-24T06:47:42Z","timestamp":1750747662722,"version":"3.37.3"},"reference-count":26,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T00:00:00Z","timestamp":1694563200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T00:00:00Z","timestamp":1694563200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002347","name":"German Federal Ministry of Education and Research (BMBF)","doi-asserted-by":"publisher","award":["16ME0127"],"award-info":[{"award-number":["16ME0127"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,13]]},"DOI":"10.1109\/fdl59689.2023.10272202","type":"proceedings-article","created":{"date-parts":[[2023,10,9]],"date-time":"2023-10-09T18:23:26Z","timestamp":1696875806000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification"],"prefix":"10.1109","author":[{"given":"Milan","family":"Funck","sequence":"first","affiliation":[{"name":"Cyber-Physical Systems, DFKI GmbH,Bremen,Germany"}]},{"given":"Sallar","family":"Ahmadi-Pour","sequence":"additional","affiliation":[{"name":"Institute of Computer Science, University of Bremen,Bremen,Germany"}]},{"given":"Vladimir","family":"Herdt","sequence":"additional","affiliation":[{"name":"Cyber-Physical Systems, DFKI GmbH,Bremen,Germany"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"Cyber-Physical Systems, DFKI GmbH,Bremen,Germany"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2022.102757"},{"journal-title":"Examples of bugs found by riscv-formal","year":"0","key":"ref12"},{"journal-title":"Axiomising RISC-V processors through formal verification","year":"2022","key":"ref15"},{"journal-title":"OneSpin 360 DV RISC-V Verification App","year":"2020","key":"ref14"},{"journal-title":"A FPGA friendly 32 bit RISC-V CPU implementation","year":"0","key":"ref11"},{"journal-title":"PicoRV32 - A Size-Optimized RISC-V CPU","year":"0","key":"ref10"},{"journal-title":"The RISC-V Instruction Set Manual Volume II Privileged Architecture","year":"2019","author":"waterman","key":"ref2"},{"journal-title":"The RISC-V instruction set manual volume i Unprivileged ISA","year":"2019","author":"waterman","key":"ref1"},{"journal-title":"Formal specification of RISC-V ISA in kami","year":"2022","key":"ref17"},{"journal-title":"Democratising formal verification of RISC-V processors","year":"2019","key":"ref16"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2010.62"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116515"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431584"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2012.6398362"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-39724-3_11"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC53125.2021.9606997"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/PRDC.2011.47"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TAIC.PART.2007.39"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341472"},{"journal-title":"riscv-dv","year":"0","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2018.00011"},{"journal-title":"RISC-V formal verification framework","year":"2020","key":"ref9"},{"journal-title":"RISC-V foundation architecture test","year":"0","key":"ref4"},{"journal-title":"RISC-V ISA Tests","year":"0","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218629"},{"journal-title":"RISC-V Torture Test Generator","year":"0","key":"ref5"}],"event":{"name":"2023 Forum on Specification & Design Languages (FDL)","start":{"date-parts":[[2023,9,13]]},"location":"Turin, Italy","end":{"date-parts":[[2023,9,15]]}},"container-title":["2023 Forum on Specification & Design Languages (FDL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10272030\/10272044\/10272202.pdf?arnumber=10272202","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,30]],"date-time":"2023-10-30T18:38:29Z","timestamp":1698691109000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10272202\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,13]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/fdl59689.2023.10272202","relation":{},"subject":[],"published":{"date-parts":[[2023,9,13]]}}}