{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:00:33Z","timestamp":1725519633236},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1109\/fmcad.2009.5351123","type":"proceedings-article","created":{"date-parts":[[2009,12,11]],"date-time":"2009-12-11T18:55:16Z","timestamp":1260557716000},"page":"180-183","source":"Crossref","is-referenced-by-count":0,"title":["Industrial strength refinement checking"],"prefix":"10.1109","author":[{"given":"Jesse","family":"Bingham","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Erickson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gaurav","family":"Singh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Flemming","family":"Andersen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.94"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-6423(99)00030-1"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347955"},{"key":"11","article-title":"The intel quickpath interconnect architecture","author":"maddox","year":"2009","journal-title":"Dr Dobb's Journal"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1367045.1367054"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1022965204416"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(91)90224-P"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-002-0087-0"},{"key":"10","first-page":"657","article-title":"What good is temporal logic?","author":"lamport","year":"1983","journal-title":"Information Processing"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2005.1487887"},{"key":"6","article-title":"Hierarchical cache coherence protocol verification one level at a time through assume guarantee","author":"chen","year":"2007","journal-title":"Proc IEEE Int High Level Design Validation and Test Workshop (HLDVT)"},{"key":"5","first-page":"68","article-title":"Automatic verification of pipelined microprocessor control","author":"burch","year":"1994","journal-title":"6th Intl Conf on Computer-Aided Verification (CAV)"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391675"},{"key":"9","doi-asserted-by":"crossref","first-page":"170","DOI":"10.1007\/11513988_19","article-title":"Formal verification of pentium \ufffd 4 components with symbolic simulation and inductive invariants","author":"kaivola","year":"2005","journal-title":"Int Conf Computer-Aided Verification"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276232"}],"event":{"name":"2009 Formal Methods in Computer-Aided Design (FMCAD)","start":{"date-parts":[[2009,11,15]]},"location":"Austin, TX, USA","end":{"date-parts":[[2009,11,18]]}},"container-title":["2009 Formal Methods in Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5344684\/5351113\/05351123.pdf?arnumber=5351123","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T02:43:27Z","timestamp":1497840207000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5351123\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fmcad.2009.5351123","relation":{},"subject":[],"published":{"date-parts":[[2009,11]]}}}