{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:47:45Z","timestamp":1729676865242,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1109\/fmcad.2009.5351132","type":"proceedings-article","created":{"date-parts":[[2009,12,11]],"date-time":"2009-12-11T13:55:16Z","timestamp":1260539716000},"page":"128-135","source":"Crossref","is-referenced-by-count":4,"title":["Verifying equivalence of memories using a first order logic theorem prover"],"prefix":"10.1109","author":[{"given":"Zurab","family":"Khasidashvili","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmoud","family":"Kinanah","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrei","family":"Voronkov","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"19"},{"key":"22","first-page":"91","article-title":"The design and implementation of Vampire","volume":"15","author":"riazanov","year":"2002","journal-title":"AI communications"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320121"},{"year":"0","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74915-8_19"},{"journal-title":"Decision Procedures Springer EATCS","year":"2008","author":"kroening","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375153"},{"journal-title":"iProver-an instantiation-based theorem prover for first-order logic (system description)","year":"2008","author":"korovin","key":"14"},{"journal-title":"Seqver A sequential squivalence serifier for hardware designs ICCD","year":"2006","author":"kaiss","key":"11"},{"journal-title":"A compositional theory for post-reboot observational equivalence checking of hardware FMCAD","year":"2009","author":"khasidashvili","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167582"},{"journal-title":"Computing Finite Models by Reduction to Function-Free Clause Logic Journal of Applied Logic","year":"2007","author":"baumgartner","key":"3"},{"journal-title":"Proof systems for effectively propo-sitional logic","year":"2008","author":"navarro-perez","key":"20"},{"journal-title":"Scalable sequential equivalence checking across arbitrary design transformations ICCD","year":"2006","author":"baumgartner","key":"2"},{"journal-title":"A refinement method for validity checking of quantified first-order formulas in hardware verification FMCAD","year":"2006","author":"abu-haimed","key":"1"},{"key":"10","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5693-0","author":"huang","year":"1998","journal-title":"Formal Equivalence Checking and Design Debugging"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185273"},{"journal-title":"What's decidable about arrays? VMCAI","year":"2006","author":"bradley","key":"6"},{"journal-title":"Word-level sequential memory abstraction for model checking FMCAD","year":"2008","author":"bjesse","key":"5"},{"year":"0","key":"4"},{"journal-title":"Verification of embedded memory systems using efficient memory modelling DATE","year":"2005","author":"gannai","key":"9"},{"journal-title":"Model checking","year":"1999","author":"clarke","key":"8"}],"event":{"name":"2009 Formal Methods in Computer-Aided Design (FMCAD)","start":{"date-parts":[[2009,11,15]]},"location":"Austin, TX, USA","end":{"date-parts":[[2009,11,18]]}},"container-title":["2009 Formal Methods in Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5344684\/5351113\/05351132.pdf?arnumber=5351132","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T22:43:29Z","timestamp":1497825809000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5351132\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/fmcad.2009.5351132","relation":{},"subject":[],"published":{"date-parts":[[2009,11]]}}}