{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:18:34Z","timestamp":1730222314275,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fmcad.2015.7542267","type":"proceedings-article","created":{"date-parts":[[2016,8,15]],"date-time":"2016-08-15T16:28:56Z","timestamp":1471278536000},"page":"168-175","source":"Crossref","is-referenced-by-count":7,"title":["Transaction flows and executable models: formalization and analysis of message-passing protocols"],"prefix":"10.1109","author":[{"given":"Muralidhar","family":"Talupur","sequence":"first","affiliation":[]},{"given":"Sandip","family":"Ray","sequence":"additional","affiliation":[]},{"given":"John","family":"Erickson","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"1995","key":"ref10","article-title":"Message Sequence Chart (MSC) Annex B: Algebraic Semantics of Message Sequence Charts, ITU-TS, Geneva"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2008.ECP.14"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2009.5351126"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45319-9_7"},{"key":"ref14","article-title":"The Stanford FLASH Multiprocessor","author":"kustin","year":"1994","journal-title":"Proceedings of the 21st Annual InternationalSymposium on Computer Architecture (ICSA 1994)"},{"article-title":"Flows and Murphi Models for German and Flash Protocols","year":"2014","author":"talupur","key":"ref15"},{"key":"ref16","article-title":"Tools for constructing requirements specifications: the SCR Toolset at the age of nine","volume":"20","author":"heitmeyer","year":"2005","journal-title":"Computer Systems Science & Engineering"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011227529550"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2491956.2462174"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-13338-6_7"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1400751.1400854"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1646353.1646374"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/360051.360224"},{"key":"ref5","article-title":"Tutorial on Verification of Distributed Cache Memory Protocol","author":"german","year":"2004","journal-title":"5th InternationalConference on Formal Methods in Computer-Aided Design (FMC AD 2004)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276232"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1977.229904"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44585-4_25"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02658-4_32"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/32.588521"}],"event":{"name":"2015 Formal Methods in Computer-Aided Design (FMCAD)","start":{"date-parts":[[2015,9,27]]},"location":"Austin, TX, USA","end":{"date-parts":[[2015,9,30]]}},"container-title":["2015 Formal Methods in Computer-Aided Design (FMCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7539356\/7542233\/07542267.pdf?arnumber=7542267","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T16:54:13Z","timestamp":1489769653000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7542267\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/fmcad.2015.7542267","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}