{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:15:45Z","timestamp":1730222145515,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpga.2003.1227242","type":"proceedings-article","created":{"date-parts":[[2003,10,31]],"date-time":"2003-10-31T09:39:17Z","timestamp":1067593157000},"page":"62-68","source":"Crossref","is-referenced-by-count":7,"title":["Accelerating bit error rate testing using a system level design tool"],"prefix":"10.1109","author":[{"given":"V.","family":"Singh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Root","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Hemphill","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Shirazi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Hwang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Xilinx Data Sheet Reed-Solomon Encoder V3 0","year":"2002","key":"ref10"},{"journal-title":"Xilinx Data Sheet Interleaver\/De-lnterleaver V2 0","year":"2002","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PACRIM.2001.953647"},{"key":"ref13","article-title":"Design Techniques of FPGA Based Random Number Generator","author":"chu","year":"1999","journal-title":"Military and Aerospace Applications of Programmable Devices and Technologies Conference"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707895"},{"journal-title":"Alpha Data Systems Simulink Board Support Blockset","year":"0","key":"ref15"},{"journal-title":"Lyr Signal Processing DSP Link FPGA Link DSP + FPGA co-design hardware-in-the-loop co-simulation","year":"0","key":"ref16"},{"journal-title":"ANSI\/SCTE 07","year":"2000","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_117"},{"journal-title":"Error Control Coding Fundamentals and Applications","year":"1983","author":"lin","key":"ref6"},{"key":"ref5","first-page":"2001","article-title":"Digital Video Broadcasting (DVB)","volume":"300","year":"0","journal-title":"Framing Structure Channel Coding and Modulation for Digital Terrestrial Television"},{"journal-title":"Xilinx Data Sheet Viterbi Decoder V2 0","year":"2002","key":"ref8"},{"journal-title":"Xilinx Data Sheet Convolution Encoder V2 0","year":"2002","key":"ref7"},{"key":"ref2","first-page":"534","article-title":"System Level Tools for DSP in FPGAs","author":"hwang","year":"2001","journal-title":"FPL 2001 Lecture Notes in Computer Science"},{"year":"1999","key":"ref1","article-title":"Simulink, Dynamic System Simulation for Matlab, Using Simulink"},{"journal-title":"Xilinx Data Sheet Reed-Solomon Encoder V3 0","year":"2002","key":"ref9"}],"event":{"name":"11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. FCCM 2003","acronym":"FPGA-03","location":"Napa, CA, USA"},"container-title":["11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8700\/27544\/01227242.pdf?arnumber=1227242","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T14:01:47Z","timestamp":1489413707000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1227242\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/fpga.2003.1227242","relation":{},"subject":[]}}