{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T10:23:14Z","timestamp":1770286994616,"version":"3.49.0"},"reference-count":16,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpga.2003.1227249","type":"proceedings-article","created":{"date-parts":[[2003,10,31]],"date-time":"2003-10-31T09:39:17Z","timestamp":1067593157000},"page":"133-142","source":"Crossref","is-referenced-by-count":51,"title":["The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets"],"prefix":"10.1109","author":[{"given":"M.","family":"Wirthlin","sequence":"first","affiliation":[]},{"given":"E.","family":"Johnson","sequence":"additional","affiliation":[]},{"given":"N.","family":"Rollins","sequence":"additional","affiliation":[]},{"given":"M.","family":"Caffrey","sequence":"additional","affiliation":[]},{"given":"P.","family":"Graham","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"197","article-title":"Triple module redundancy design techniques for Virtex FPGAs","author":"carmichael","year":"2001","journal-title":"Technical Report"},{"key":"ref11","first-page":"216","article-title":"Correcting single-event upsets through Virtex partial configuration","author":"carmichael","year":"2000","journal-title":"Technical Report"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1987.4337512"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/23.124151"},{"key":"ref14","year":"2000","journal-title":"SLAAC-1V User VHDL Guide"},{"key":"ref15","author":"golomb","year":"1967","journal-title":"Shift Register Sequences"},{"key":"ref16","article-title":"Virtex Series Configuration Architecture User Guide","year":"2000","journal-title":"Xilinx Application Notes 151 v1 5"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/23.658966"},{"key":"ref3","first-page":"68","article-title":"Single-event upset simulation on an FPG A","author":"johnson","year":"2002","journal-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)"},{"key":"ref6","first-page":"181","article-title":"SEU mitigation design techniques for the XQR4000XL","author":"brinkley","year":"2000","journal-title":"Technical Report"},{"key":"ref5","first-page":"30p","article-title":"Radiation testing update, seu mitigation, and availability analysis of the Virtex FPGA for space reconfigurable computing","author":"fuller","year":"2000","journal-title":"4th Annual Conference on Military and Aerospace Programmable Logic Devices (MAPLD)"},{"key":"ref8","author":"baylis","year":"1997","journal-title":"Error Correcting Codes A Mathematical Introduction"},{"key":"ref7","article-title":"A fault injection analysis of Virtex FPGA TMR design methodology","author":"lima","year":"2001","journal-title":"Proceedings of the 6th European Conference on Radiation and its Effects on Components and Sysemts (RADECS 2001)"},{"key":"ref2","article-title":"Radiation test results of the Virtex FPGA and ZBT SRAM for space based reconfigurable computing","author":"fuller","year":"1999","journal-title":"MAPLD Proceedings"},{"key":"ref1","first-page":"49","article-title":"A space-based reconfigurable radio","author":"caffrey","year":"2002","journal-title":"Proceedings of the International Conference on Engineering of Reconfigurable Systems and Al-gorithms (ERSA)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2003.1235164"}],"event":{"name":"11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. FCCM 2003","location":"Napa, CA, USA","acronym":"FPGA-03"},"container-title":["11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8700\/27544\/01227249.pdf?arnumber=1227249","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T15:11:56Z","timestamp":1489417916000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1227249\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/fpga.2003.1227249","relation":{},"subject":[]}}