{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:15:53Z","timestamp":1730222153576,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpl.2005.1515692","type":"proceedings-article","created":{"date-parts":[[2005,10,12]],"date-time":"2005-10-12T13:27:51Z","timestamp":1129123671000},"page":"13-18","source":"Crossref","is-referenced-by-count":2,"title":["Low-cost fully reconfigurable data-path for FPGA-based multimedia processor"],"prefix":"10.1109","author":[{"given":"M.","family":"Lanuzza","sequence":"first","affiliation":[]},{"given":"S.","family":"Perri","sequence":"additional","affiliation":[]},{"given":"M.","family":"Margala","sequence":"additional","affiliation":[]},{"given":"P.","family":"Corsonello","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Digital Computer Arithmetic Design and Implementation","year":"1984","author":"cavanaugh","key":"13"},{"journal-title":"Constraints Guide - ISE 5","year":"2002","key":"14"},{"key":"11","article-title":"Novel optimizations for hardware floating-point units in a modern FPGA architecture","author":"roesler","year":"2002","journal-title":"Proc Int Conf Field Program Logic Applicat (FPL)"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.833400"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275164"},{"key":"10","article-title":"Processor architectures for multimedia","author":"nazareth","year":"2001","journal-title":"Academics Paper"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2004.03.015"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45234-8_23"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/EMPDP.2001.905048"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSP.2002.1028324"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1117\/12.334763"},{"key":"8","article-title":"IEEE standard for binary floating-point arithmetic","volume":"754","year":"1985","journal-title":"ANSI\/IEEE Standard No 754-1985"}],"event":{"name":"International Conference on Field Programmable Logic and Applications, 2005.","location":"Tampere, Finland"},"container-title":["International Conference on Field Programmable Logic and Applications, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10158\/32467\/01515692.pdf?arnumber=1515692","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T17:33:51Z","timestamp":1489512831000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1515692\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/fpl.2005.1515692","relation":{},"subject":[]}}