{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:15:56Z","timestamp":1730222156292,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpl.2005.1515699","type":"proceedings-article","created":{"date-parts":[[2005,10,12]],"date-time":"2005-10-12T17:27:51Z","timestamp":1129138071000},"page":"57-64","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processor"],"prefix":"10.1109","author":[{"family":"Chi-Wei Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.P.","family":"Carter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.B.","family":"Kujoth","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.J.","family":"Cook","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.B.","family":"Gottlieb","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1999.765937"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1999.756035"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968284"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968309"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2002.1188674"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360323"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003558"},{"journal-title":"SIA Memo FO4 Writeup","year":"2003","key":"6"},{"journal-title":"The International Technology Roadmap for Semiconductors","year":"2001","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296442"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360331"},{"key":"8","article-title":"CACTI 3.0: An integrated cache timing, power, and area model","volume":"2001","author":"shivakumar","year":"2001","journal-title":"Tech Rep"}],"event":{"name":"International Conference on Field Programmable Logic and Applications, 2005.","location":"Tampere, Finland"},"container-title":["International Conference on Field Programmable Logic and Applications, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10158\/32467\/01515699.pdf?arnumber=1515699","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T20:09:53Z","timestamp":1489522193000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1515699\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/fpl.2005.1515699","relation":{},"subject":[]}}