{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T15:50:58Z","timestamp":1742399458543},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpl.2005.1515716","type":"proceedings-article","created":{"date-parts":[[2005,10,12]],"date-time":"2005-10-12T17:27:51Z","timestamp":1129138071000},"page":"159-166","source":"Crossref","is-referenced-by-count":2,"title":["Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks"],"prefix":"10.1109","author":[{"given":"A.","family":"Ye","sequence":"first","affiliation":[]},{"given":"J.","family":"Rose","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1961.5219222"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393260"},{"journal-title":"Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits","year":"2004","author":"ye","key":"18"},{"journal-title":"Xilinx Data Sheet","year":"2004","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2002.1188685"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"journal-title":"Altera Documentation Library","year":"2004","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"12","first-page":"195","article-title":"An FPGA architecture with enhanced datapath functionality","author":"leijten-nowak","year":"2003","journal-title":"FPGA"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275134"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/92.475966"},{"key":"22","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1145\/329166.329201","article-title":"New parallelization and convergence results for NC: A negotiation-based FPGA router","author":"chan","year":"2000","journal-title":"FPGA"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249360"},{"key":"24","doi-asserted-by":"crossref","DOI":"10.1145\/1046192.1046194","article-title":"Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits","author":"ye","year":"2005","journal-title":"FPGA"},{"journal-title":"Pica-java Processor Design Documentation","year":"1999","key":"25"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1990.124841"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258315"},{"key":"2","first-page":"169","article-title":"A reconfigurable data driven multi-processor architecture for rapid prototyping of high throughput DSP algorithms","author":"yeung","year":"1993","journal-title":"HICCS"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2000.903407"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/4.173120"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"6","first-page":"24","article-title":"Garp: A MIPS processor with a reconfigurable coprocessor","author":"hauser","year":"1997","journal-title":"FCCM"},{"key":"5","first-page":"237","article-title":"RaPiD -reconfigurable pipelined datapath","author":"ebeling","year":"1996","journal-title":"FPL"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1155\/1996\/95942"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296444"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707876"}],"event":{"name":"International Conference on Field Programmable Logic and Applications, 2005.","location":"Tampere, Finland"},"container-title":["International Conference on Field Programmable Logic and Applications, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10158\/32467\/01515716.pdf?arnumber=1515716","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,5]],"date-time":"2023-05-05T02:16:53Z","timestamp":1683253013000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1515716\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/fpl.2005.1515716","relation":{},"subject":[]}}