{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:20:56Z","timestamp":1729610456667,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpl.2005.1515778","type":"proceedings-article","created":{"date-parts":[[2005,10,12]],"date-time":"2005-10-12T17:27:51Z","timestamp":1129138071000},"page":"531-534","source":"Crossref","is-referenced-by-count":0,"title":["Efficient embedded FPL resource usage for RNS-based polyphase DWT filter banks"],"prefix":"10.1109","author":[{"given":"A.","family":"Garcia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Ramirez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Castillo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Lloris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"U.","family":"Meyer-Baese","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"Fast residual arithmetic with FPGAs","author":"hamann","year":"1995","journal-title":"Proc Design Methodologies for Microelectronics"},{"key":"2","doi-asserted-by":"crossref","first-page":"472","DOI":"10.1007\/3-540-46117-5_50","article-title":"Fast RNS-based FPL communications receiver design and implementation","volume":"2438","author":"rami?rez","year":"2002","journal-title":"Lecture Notes in Computer Science"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1080\/00207219108921278"},{"journal-title":"Residue Number System Arithmetic Modern Applications in Digital Signal Processing","year":"1986","author":"soderstrand","key":"1"},{"key":"7","doi-asserted-by":"crossref","first-page":"115","DOI":"10.1023\/A:1008167323437","article-title":"Implementation of a communications channelizer using FPGAs and RNS arithmetic","volume":"28","author":"meyer-baese","year":"2001","journal-title":"Journal of VLSI Signal Processing"},{"key":"6","article-title":"FPGAs: The high-end alternative for DSP applications","author":"dick","year":"2000","journal-title":"DSP Engineering"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1049\/el:20020129"},{"key":"4","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1023\/A:1023296218588","article-title":"Design and implementation of high-performance RNS wavelet processors using custom IC technologies","volume":"34","author":"rami?rez","year":"2003","journal-title":"Journal of VLSI Signal Processing"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1993.692781"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1996.599104"},{"journal-title":"Wavelets and Subband Coding","year":"1995","author":"vetterli","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1989.266618"}],"event":{"name":"International Conference on Field Programmable Logic and Applications, 2005.","location":"Tampere, Finland"},"container-title":["International Conference on Field Programmable Logic and Applications, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10158\/32467\/01515778.pdf?arnumber=1515778","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T00:02:57Z","timestamp":1497657777000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1515778\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/fpl.2005.1515778","relation":{},"subject":[]}}