{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T19:45:40Z","timestamp":1747856740889},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1109\/fpl.2005.1515782","type":"proceedings-article","created":{"date-parts":[[2005,10,12]],"date-time":"2005-10-12T17:27:51Z","timestamp":1129138071000},"page":"547-550","source":"Crossref","is-referenced-by-count":1,"title":["FPGA implementation of an area-time efficient FIR filter core using a self-clocked approach"],"prefix":"10.1109","author":[{"given":"J.","family":"Javier Martinez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Javier Toledo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Javier Garrigos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Manuel Ferrdndez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"517","article-title":"Sincronizacio?n self-timed: Protocolo de 4 fases","author":"ortega","year":"2003","journal-title":"JCRA Jornadas de Computation Reconfigurable y Aplicaciones"},{"key":"2","first-page":"503","article-title":"Sincronizacio?n self-timed: Protocole de 2 fases","author":"boemo","year":"2003","journal-title":"JCRA Jornadas de Computation Reconfigurable y Aplicaciones"},{"key":"1","first-page":"423","article-title":"Fpga-based implementation of the instantaneous frequency estimation of phonocardiographic signals","author":"herna?ndez","year":"2004","journal-title":"IFAC Workshop on Programmable Devices and Systems"},{"key":"7","article-title":"Principles of asynchronous circuit design a systems perspective","author":"sparso","year":"2001","journal-title":"European Low-Power Initiative for Electronic System Design"},{"key":"6","article-title":"A self clocked fpga for general purpose logic emulation","author":"dana","year":"1996","journal-title":"Proc IEEE Custom Integrated Circuits Conference"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/92.502196"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/5.362752"},{"journal-title":"Xilinx Core Generator Data Sheet(ds245) Mac-fir V5 0","year":"2004","key":"8"}],"event":{"name":"Proceedings. 2005 International Conference on Field Programmable Logic and Applications","start":{"date-parts":[[2005,8,24]]},"location":"Tampere","end":{"date-parts":[[2005,8,26]]}},"container-title":["International Conference on Field Programmable Logic and Applications, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10158\/32467\/01515782.pdf?arnumber=1515782","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T21:41:26Z","timestamp":1489527686000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1515782\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/fpl.2005.1515782","relation":{},"subject":[],"published":{"date-parts":[[2005]]}}}