{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T12:08:59Z","timestamp":1725538139071},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/fpl.2005.1515808","type":"proceedings-article","created":{"date-parts":[[2005,10,12]],"date-time":"2005-10-12T13:27:51Z","timestamp":1129123671000},"page":"662-665","source":"Crossref","is-referenced-by-count":0,"title":["Coping with uncertainty in FPGA architecture design"],"prefix":"10.1109","author":[{"given":"B.","family":"Ratchev","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Hutton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Mendel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503071"},{"journal-title":"Statistical Analysis and Optimization for VLSI Timing and Power","year":"2005","author":"srivastava","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219021"},{"key":"3","first-page":"135","article-title":"Improving FPGA performance and area using an adaptive logic module","author":"hutton","year":"0","journal-title":"Proc FPL 2004"},{"key":"2","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1145\/329166.329203","article-title":"Automatic generation of FPGA architectures","author":"betz","year":"2000","journal-title":"Proc FPGA"},{"key":"1","first-page":"213","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"0","journal-title":"Proc FPL 1997"},{"journal-title":"Resampling The New Statistics","year":"1974","author":"simon","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/639929.639936"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/611843.611844"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"4","first-page":"12","article-title":"The stratix TM routing and logic architecture","author":"lewis","year":"0","journal-title":"Proc FPGA 2003"},{"journal-title":"Sam Savage's Online Tutorial on Understanding Uncertainty","year":"0","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/4.62145"}],"event":{"name":"International Conference on Field Programmable Logic and Applications, 2005.","location":"Tampere, Finland"},"container-title":["International Conference on Field Programmable Logic and Applications, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10158\/32467\/01515808.pdf?arnumber=1515808","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T20:02:58Z","timestamp":1497643378000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1515808\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/fpl.2005.1515808","relation":{},"subject":[]}}