{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:20:30Z","timestamp":1742383230323,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/fpl.2007.4380630","type":"proceedings-article","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T21:56:42Z","timestamp":1194991002000},"page":"86-91","source":"Crossref","is-referenced-by-count":4,"title":["Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems"],"prefix":"10.1109","author":[{"given":"Yi-Gang","family":"Tai","sequence":"first","affiliation":[]},{"given":"Chia-Tien Dan","family":"Lo","sequence":"additional","affiliation":[]},{"given":"Kleanthis","family":"Psarris","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1137\/S0036144503428693"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898719604"},{"journal-title":"IBM CoreConnect bus architecture A 32- 64- 128-bit core on-chip bus structure","year":"0","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1055531.1055534"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1999.803667"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1065895.1065898"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SC.1998.10004"},{"key":"ref8","first-page":"286","article-title":"An FPGA-based computation model for blocked algorithms","author":"tai","year":"2006","journal-title":"AIC '06 6th WSEAS International Conference on Applied Informatics and Communications"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270354"},{"article-title":"High fidelity deconvolution of moderately resolved sources","year":"1995","author":"briggs","key":"ref2"},{"key":"ref9","first-page":"2977","article-title":"FPGA-based hardware acceleration on I\/O-bound scientific applications","volume":"5","author":"lo","year":"2006","journal-title":"WSEAS Transactions on Computers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611971217"}],"event":{"name":"2007 International Conference on Field Programmable Logic and Applications","start":{"date-parts":[[2007,8,27]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2007,8,29]]}},"container-title":["2007 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4380601\/4380602\/04380630.pdf?arnumber=4380630","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T20:52:40Z","timestamp":1643748760000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4380630\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/fpl.2007.4380630","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}