{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T02:16:46Z","timestamp":1725675406919},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/fpl.2007.4380647","type":"proceedings-article","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T21:56:42Z","timestamp":1194991002000},"page":"196-201","source":"Crossref","is-referenced-by-count":16,"title":["Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications"],"prefix":"10.1109","author":[{"given":"Chun Hok","family":"Ho","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi Wai","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philip H.W.","family":"Leong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Luk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J.E.","family":"Wilton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"637","article-title":"Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture","author":"roesler","year":"2002","journal-title":"Proc FPL"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.876095"},{"journal-title":"Floating-point operator v3 0 Product specification","year":"2005","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.71"},{"key":"ref11","article-title":"Single event upset susceptibility testing of the Xilinx Virtex II FPGA","author":"yui","year":"2002","journal-title":"Military Aerosp Appl Program Logic Conf (MAPLD)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117204"},{"key":"ref8","first-page":"61","article-title":"ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix","author":"mei","year":"2003","journal-title":"Proc FPL"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref2","first-page":"111","article-title":"Totem: Custom Reconfigurable Array Generation","author":"compton","year":"2001","journal-title":"Proc FCCM"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216924"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1117201.1117205"}],"event":{"name":"2007 International Conference on Field Programmable Logic and Applications","start":{"date-parts":[[2007,8,27]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2007,8,29]]}},"container-title":["2007 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4380601\/4380602\/04380647.pdf?arnumber=4380647","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T20:52:15Z","timestamp":1643748735000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4380647\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/fpl.2007.4380647","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}