{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T09:40:16Z","timestamp":1790070016758,"version":"4.0.1"},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,8]]},"DOI":"10.1109\/fpl.2007.4380648","type":"proceedings-article","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T21:56:42Z","timestamp":1194991002000},"page":"202-209","source":"Crossref","is-referenced-by-count":2,"title":["Embedded Programmable Logic Core Enhancements for System Bus Interfaces"],"prefix":"10.1109","author":[{"given":"Bradley R.","family":"Quinton","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Steven J.E.","family":"Wilton","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270384"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.826825"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2005.39"},{"key":"ref13","article-title":"Rapid Prototping of Electronic Systems Using FIPSOC","author":"madrenas","year":"1999","journal-title":"Proc IEEE Conf on Emerging Technologies and Factory Automation"},{"key":"ref14","article-title":"Progammable Logic IP Cores in SoC Design: Opportunities and Challenges","author":"wilton","year":"2001","journal-title":"Proc IEEE Custom IC Conf"},{"key":"ref15","article-title":"A Hybrid ASIC and FPGA Architecture","author":"zuchowski","year":"2002","journal-title":"Proc IEEEIACM Int Conf on Computer-Aided Design"},{"key":"ref16","doi-asserted-by":"crossref","DOI":"10.1145\/775832.775943","article-title":"System-on-Chip Beyond the Nanometer Wall","author":"magarshack","year":"2003","journal-title":"Proc Design Automation Conference"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2005.023"},{"key":"ref4","year":"0","journal-title":"M2000 FLEXEOS Configurable IP Core"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503073"},{"key":"ref6","year":"2002","journal-title":"Opencores org Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores Revision B 3"},{"key":"ref5","year":"0","journal-title":"EASIC 0 13um Core"},{"key":"ref8","year":"2006","journal-title":"Device Control Register Bus 3 5 Architecture Specifications"},{"key":"ref7","year":"2001","journal-title":"On-chip Peripheral Bus Architecture Specification Version 2 1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.841038"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2005.1568553"},{"key":"ref9","year":"1999","journal-title":"AMBA Specification Revision 2 0"}],"event":{"name":"2007 International Conference on Field Programmable Logic and Applications","location":"Amsterdam, Netherlands","start":{"date-parts":[[2007,8,27]]},"end":{"date-parts":[[2007,8,29]]}},"container-title":["2007 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4380601\/4380602\/04380648.pdf?arnumber=4380648","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T20:52:18Z","timestamp":1643748738000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4380648\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/fpl.2007.4380648","relation":{},"subject":[],"published":{"date-parts":[[2007,8]]}}}