{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T03:47:38Z","timestamp":1780372058897,"version":"3.54.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1109\/fpl.2008.4629937","type":"proceedings-article","created":{"date-parts":[[2008,9,26]],"date-time":"2008-09-26T11:16:55Z","timestamp":1222427815000},"page":"233-238","source":"Crossref","is-referenced-by-count":13,"title":["A technique for minimizing power during FPGA placement"],"prefix":"10.1109","author":[{"given":"Kristofer","family":"Vorwerk","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Madhu","family":"Raman","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Julien","family":"Dunoyer","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yaun-chung Hsu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arun","family":"Kundu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrew","family":"Kennings","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"2","first-page":"211","article-title":"power-aware technology mapping for lut-based fpgas","author":"anderson","year":"2002","journal-title":"Proc FPT"},{"key":"10","year":"0"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405687"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159755"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/31605"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380636"},{"key":"4","first-page":"79","author":"kang","year":"2006","journal-title":"Low-power clustering with minimum logic replication for coarse-grained antifuse based FPGAs"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065791"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2004.1337686"},{"key":"11","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"vpr: a new packing, placement and routing tool for fpga research","author":"betz","year":"1997","journal-title":"Field-Programmable Logic and Applications"}],"event":{"name":"2008 International Conference on Field Programmable Logic and Applications (FPL)","location":"Heidelberg, Germany","start":{"date-parts":[[2008,9,8]]},"end":{"date-parts":[[2008,9,10]]}},"container-title":["2008 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4625340\/4629890\/04629937.pdf?arnumber=4629937","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T08:05:04Z","timestamp":1497773104000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4629937\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/fpl.2008.4629937","relation":{},"subject":[],"published":{"date-parts":[[2008]]}}}