{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T14:15:20Z","timestamp":1761488120171},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1109\/fpl.2008.4629964","type":"proceedings-article","created":{"date-parts":[[2008,9,26]],"date-time":"2008-09-26T11:16:55Z","timestamp":1222427815000},"page":"361-366","source":"Crossref","is-referenced-by-count":16,"title":["Automatic generation of run-time parameterizable configurations"],"prefix":"10.1109","author":[{"given":"Karel","family":"Bruneel","sequence":"first","affiliation":[]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380622"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1023\/B:VLSI.0000008066.95259.b8"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564830"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0055257"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564749"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1142980.1142986"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707896"},{"key":"5","first-page":"1068","article-title":"data dependent circuit for subgraph isomorphism problem","author":"ichikawa","year":"2002","journal-title":"Proc Int'l Conf Field-Programmable Logic and Applications (FPL '05)"},{"key":"4","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1007\/3-540-63465-7_220","article-title":"a case study of partially evaluated hardware circuits: key-specific des","author":"leonard","year":"1997","journal-title":"Proc Int Field Programmable Logic Appl (FPL)"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/92.678880"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296449"}],"event":{"name":"2008 International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2008,9,8]]},"location":"Heidelberg, Germany","end":{"date-parts":[[2008,9,10]]}},"container-title":["2008 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4625340\/4629890\/04629964.pdf?arnumber=4629964","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T08:05:04Z","timestamp":1497773104000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4629964\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/fpl.2008.4629964","relation":{},"subject":[],"published":{"date-parts":[[2008]]}}}