{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,30]],"date-time":"2024-12-30T18:18:33Z","timestamp":1735582713623},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,8]]},"DOI":"10.1109\/fpl.2009.5272250","type":"proceedings-article","created":{"date-parts":[[2009,9,30]],"date-time":"2009-09-30T14:42:09Z","timestamp":1254321729000},"page":"403-409","source":"Crossref","is-referenced-by-count":7,"title":["IP protection in Partially Reconfigurable FPGAs"],"prefix":"10.1109","author":[{"given":"Krzysztof","family":"Kepa","sequence":"first","affiliation":[]},{"given":"Fearghal","family":"Morgan","sequence":"additional","affiliation":[]},{"given":"Krzysztof","family":"Kosciuszkiewicz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Virtex-5 User Guide UG191 (v3 6)","year":"2009","key":"19"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405689"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2007.36"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2007.28"},{"journal-title":"Low temperature data remanence in static RAM","year":"2002","author":"skorobogatov","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00641-8_8"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00641-8_9"},{"key":"11","first-page":"287","article-title":"dynamic intellectual proper ty protection for reconfigurable devices","author":"guneysu","year":"2007","journal-title":"Proc of the 15th Annual IEEE Symposium on FPT"},{"year":"0","key":"12"},{"journal-title":"AES (Rijndael) IP Core","year":"0","author":"usselmann","key":"21"},{"key":"3","article-title":"designing and implementing malicious hardware","author":"king","year":"2008","journal-title":"First USENIX Workshop on Large-Scale Exploits and Emergent Threats (LEET)"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-71431-6_7"},{"journal-title":"Volatile FPGA design security - a survey","year":"2007","author":"drimer","key":"2"},{"year":"0","key":"1"},{"article-title":"ip security in fpgas","year":"2007","author":"lesea","key":"10"},{"year":"0","key":"7"},{"year":"0","key":"6"},{"key":"5","article-title":"serecon: a secure reconfiguration controller for self-reconfigurable systems","author":"kepa","year":"2009","journal-title":"Special issue of International Journal of Critical Computer-Based Systems (IJCCBS) devoted to DepCoS-2008 conference"},{"key":"4","article-title":"fpga-based single chip cryptographic solution","author":"mclean","year":"0","journal-title":"Military Embedded Systems"},{"year":"0","key":"9"},{"journal-title":"Xilinx speeds HDL simulation with SecureIP and FAST Simulation Mode Models","year":"2008","author":"walker","key":"8"}],"event":{"name":"2009 International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2009,8,31]]},"location":"Prague, Czech Republic","end":{"date-parts":[[2009,9,2]]}},"container-title":["2009 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5247666\/5272229\/05272250.pdf?arnumber=5272250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T19:56:35Z","timestamp":1489866995000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5272250\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,8]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/fpl.2009.5272250","relation":{},"subject":[],"published":{"date-parts":[[2009,8]]}}}