{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:19:17Z","timestamp":1730222357287,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/fpl.2012.6339215","type":"proceedings-article","created":{"date-parts":[[2012,10,26]],"date-time":"2012-10-26T17:47:45Z","timestamp":1351273665000},"page":"595-598","source":"Crossref","is-referenced-by-count":2,"title":["Sliding block Viterbi decoders in FPGA"],"prefix":"10.1109","author":[{"given":"Mario","family":"Vestias","sequence":"first","affiliation":[]},{"given":"Horacio","family":"Neto","sequence":"additional","affiliation":[]},{"given":"Helena","family":"Sarmento","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"1877","article-title":"A 50 Mb\/s Multiplexed Coding System for Shuttle Communications","volume":"com 26","author":"dunn","year":"1978","journal-title":"IEEE Transactions Communication"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/4.173118"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4899-2174-1_6"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCPS.2011.6092169"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/79.410439"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377841"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1981.1095134"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.1989.49807"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/4.585246"},{"key":"8","first-page":"616","article-title":"VLSI architectures for Metric Normalization in the Viterbi algorithm design","volume":"40","author":"shung","year":"1992","journal-title":"IEEE Transaction on Communications"},{"key":"11","first-page":"258","author":"viterbi","year":"1979","journal-title":"Principles of Digital Communication and Coding"},{"key":"12","article-title":"Implementing High-Speed Viterbi Decoders for MB-OFDM on FPGA","author":"ve?stias","year":"0","journal-title":"XXV Conference on Design of Circuits and Integrated Systems 2010"}],"event":{"name":"2012 22nd International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2012,8,29]]},"location":"Oslo, Norway","end":{"date-parts":[[2012,8,31]]}},"container-title":["22nd International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6330714\/6339128\/06339215.pdf?arnumber=6339215","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T21:35:12Z","timestamp":1490132112000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6339215\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/fpl.2012.6339215","relation":{},"subject":[],"published":{"date-parts":[[2012,8]]}}}