{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T17:19:23Z","timestamp":1730222363917,"version":"3.28.0"},"reference-count":4,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/fpl.2012.6339229","type":"proceedings-article","created":{"date-parts":[[2012,10,26]],"date-time":"2012-10-26T21:47:45Z","timestamp":1351288065000},"page":"639-642","source":"Crossref","is-referenced-by-count":0,"title":["Wire-speed verification schemes for HW\/SW design of 10-Gbit\/s-class large-scale NW SoC using multiple FPGAs"],"prefix":"10.1109","author":[{"given":"Kazuhiko","family":"Terada","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Uzawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Namiko","family":"Ikeda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Shigematsu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nobuyuki","family":"Tanaka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masami","family":"Urano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"Design and implementation of a protocol offload engine for TCP\/IP and remote direct memory access based on hardware\/software coprocessing","volume":"33","author":"j","year":"0","journal-title":"Microprocessors and Microsystems"},{"key":"2","article-title":"The 10G-EPON OLT and ONU LSIs for the Coexistence of 10G-EPON and GE-PON toward the Next FTTH Era","author":"u","year":"0","journal-title":"VLSI"},{"key":"1","article-title":"An SoC demonstration of ONU discovery and dynamic bandwidth allocation for 10G\/1G dual-rate 10G-EPON OLT","author":"n","year":"0","journal-title":"OFC\/NFOEC 2011"},{"key":"4","article-title":"FPGA Design Schemeology for Communication Frame Processing","author":"k","year":"0","journal-title":"Proc of Integrated Circuits and Devices in Vietnam 2010"}],"event":{"name":"2012 22nd International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2012,8,29]]},"location":"Oslo, Norway","end":{"date-parts":[[2012,8,31]]}},"container-title":["22nd International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6330714\/6339128\/06339229.pdf?arnumber=6339229","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T01:26:24Z","timestamp":1490145984000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6339229\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/fpl.2012.6339229","relation":{},"subject":[],"published":{"date-parts":[[2012,8]]}}}