{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:03:35Z","timestamp":1729631015226,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/fpl.2012.6339245","type":"proceedings-article","created":{"date-parts":[[2012,10,26]],"date-time":"2012-10-26T17:47:45Z","timestamp":1351273665000},"page":"83-90","source":"Crossref","is-referenced-by-count":5,"title":["On the difficulty of pin-to-wire routing in FPGAs"],"prefix":"10.1109","author":[{"given":"Niyati","family":"Shah","sequence":"first","affiliation":[]},{"given":"Jonathan","family":"Rose","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"journal-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3 0","year":"1991","author":"yang","key":"17"},{"journal-title":"Cluster-based architecture timing-driven packing and timing-driven placement for FPGAs","year":"1999","author":"marquardt","key":"18"},{"journal-title":"iFAR Intelligent FPGA Architecture Repository","year":"2008","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344695"},{"journal-title":"Academic Clustering and Placement Tools for Modern Field-programmable Gate Array Architectures","year":"2008","author":"paladino","key":"13"},{"journal-title":"Architecture and CAD for Deep-Submicron FPGAs","year":"1999","author":"rose","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1854153.1854181"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393249"},{"key":"3","article-title":"Modem floorplanning with abutment and fixed-outline constraints","volume":"6","author":"lin","year":"2005","journal-title":"IEEE ISCAS"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"2","doi-asserted-by":"crossref","first-page":"327","DOI":"10.1145\/266021.266126","article-title":"Cellerity: A fully automatic layout synthesis system for standard cell libraries","author":"guruswamy","year":"1997","journal-title":"DAC"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296431"},{"journal-title":"7 Series FPGAs Overview","year":"2012","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2003.1275743"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145738"},{"journal-title":"Xilinx Partial Reconfiguration User Guide","year":"2011","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380705"},{"journal-title":"Stratix IV Device Handbook","year":"2011","key":"9"},{"journal-title":"Stratix II device handbook","year":"2011","key":"8"}],"event":{"name":"2012 22nd International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2012,8,29]]},"location":"Oslo, Norway","end":{"date-parts":[[2012,8,31]]}},"container-title":["22nd International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6330714\/6339128\/06339245.pdf?arnumber=6339245","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,4]],"date-time":"2019-07-04T21:48:25Z","timestamp":1562276905000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6339245\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/fpl.2012.6339245","relation":{},"subject":[],"published":{"date-parts":[[2012,8]]}}}