{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T07:02:48Z","timestamp":1761807768765,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/fpl.2012.6339269","type":"proceedings-article","created":{"date-parts":[[2012,10,26]],"date-time":"2012-10-26T17:47:45Z","timestamp":1351273665000},"page":"519-522","source":"Crossref","is-referenced-by-count":8,"title":["A two-stage variation-aware placement method for FPGAS exploiting variation maps classification"],"prefix":"10.1109","author":[{"given":"Zhenyu","family":"Guan","sequence":"first","affiliation":[]},{"given":"Justin S. J.","family":"Wong","sequence":"additional","affiliation":[]},{"given":"Sumanta","family":"Chaudhuri","sequence":"additional","affiliation":[]},{"given":"George","family":"Constantinides","sequence":"additional","affiliation":[]},{"given":"Peter Y. K.","family":"Cheung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Principal Component Analysis","year":"2012","key":"15"},{"journal-title":"Gaussian Function","year":"2012","key":"13"},{"journal-title":"K-Means Clustering","year":"2012","key":"14"},{"key":"11","first-page":"278","article-title":"On timing yield improvement for fpga designs using architectural symmetry","author":"yu","year":"0","journal-title":"Proc Int Conf FPGA 2011"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311193"},{"key":"3","first-page":"93","article-title":"Managing process variation in intel's 45nm CMOS technology","volume":"12","author":"kuhn","year":"2008","journal-title":"Intel Technology Journal"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216949"},{"key":"1","first-page":"338","article-title":"Parameter variations and impact on circuits and microarchitecture","author":"shekhar","year":"0","journal-title":"Proc 40th ACM Conf Design Automation 2003"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2010.5642616"},{"key":"7","first-page":"900","article-title":"Statistical timing analysis for intra-die process variations with spatial correlations","author":"aseem","year":"0","journal-title":"Proc IEEE\/ACM Int Conf Computer Aided Design 2003"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2008.4762372"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2007.4439227"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145710"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.912027"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457107"}],"event":{"name":"2012 22nd International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2012,8,29]]},"location":"Oslo, Norway","end":{"date-parts":[[2012,8,31]]}},"container-title":["22nd International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6330714\/6339128\/06339269.pdf?arnumber=6339269","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T21:26:23Z","timestamp":1490131583000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6339269\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fpl.2012.6339269","relation":{},"subject":[],"published":{"date-parts":[[2012,8]]}}}