{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T19:40:22Z","timestamp":1729626022711,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/fpl.2014.6927417","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T17:13:21Z","timestamp":1413998001000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Area implications of memory partitioning for high-level synthesis on FPGAs"],"prefix":"10.1109","author":[{"given":"Luca","family":"Gallo","sequence":"first","affiliation":[]},{"given":"Alessandro","family":"Cilardo","sequence":"additional","affiliation":[]},{"given":"David","family":"Thomas","sequence":"additional","affiliation":[]},{"given":"Samuel","family":"Bayliss","sequence":"additional","affiliation":[]},{"given":"George A.","family":"Constantinides","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.97"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.08.005"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/951746.951749"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.206"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429484"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1929943.1929947"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.352"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645494"},{"key":"9","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1109\/TCAD.2009.2013541","article-title":"Combining data reuse with data-level parallelization for FPGA-targeted hardware compilation: A geometric programming framework","volume":"28","author":"liu","year":"2009","journal-title":"Trans Comp -Aided Des Integ Cir Sys"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488748"}],"event":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2014,9,2]]},"location":"Munich, Germany","end":{"date-parts":[[2014,9,4]]}},"container-title":["2014 24th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6913605\/6927322\/06927417.pdf?arnumber=6927417","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T18:53:15Z","timestamp":1498157595000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6927417\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/fpl.2014.6927417","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}