{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T07:38:47Z","timestamp":1725608327745},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/fpl.2014.6927444","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T17:13:21Z","timestamp":1413998001000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["Ready PCIe data streaming solutions for FPGAs"],"prefix":"10.1109","author":[{"given":"Thomas B.","family":"Preusser","sequence":"first","affiliation":[]},{"given":"Rainer G.","family":"Spallek","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Riffa","year":"0","author":"jacobsen","key":"17"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/SPL.2011.5782641"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339139"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.45"},{"journal-title":"A Comparison of Specification Changes in the Recent Versions of RapidIO and PCI Express","year":"2009","author":"roddick","key":"13"},{"journal-title":"IEEE 802 3(TM) Ethernet","year":"2012","key":"14"},{"journal-title":"An FPGA IP Core for Easy DMA over PCIe with Windows and Linux","year":"0","key":"11"},{"key":"12","article-title":"RapidIO 10 year success: Stepping in when Moores Law cant keep up","author":"paul","year":"2011","journal-title":"Integrated Device Technology Tech Rep"},{"journal-title":"Designing A System Using the Aurora 8B10B Core (Duplex) on the KC705 Evaluation Kit","year":"2014","author":"kumar","key":"3"},{"journal-title":"Aurora","year":"0","key":"2"},{"journal-title":"Implementing FPGA Design with the OpenCL Standard","year":"2013","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645504"},{"journal-title":"An Introduction to the Intel QuickPath Interconnect","year":"2009","key":"7"},{"journal-title":"Xilinx Interlaken Core","year":"0","key":"6"},{"journal-title":"Interlaken Protocol Definition","year":"2008","key":"5"},{"journal-title":"Designing A System Using the Aurora 64B66B Core (Duplex) on the KC705 Evaluation Kit","year":"2014","author":"kumar","key":"4"},{"journal-title":"Pci-sig Home","year":"0","key":"9"},{"journal-title":"QuickPath Interconnect IP Enhancing Intel Processors and Accelerating Critical Server Data Paths","year":"2012","key":"8"}],"event":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2014,9,2]]},"location":"Munich, Germany","end":{"date-parts":[[2014,9,4]]}},"container-title":["2014 24th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6913605\/6927322\/06927444.pdf?arnumber=6927444","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T19:17:15Z","timestamp":1490296635000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6927444\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/fpl.2014.6927444","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}