{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:17:08Z","timestamp":1763457428193,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/fpl.2014.6927460","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T17:13:21Z","timestamp":1413998001000},"page":"1-6","source":"Crossref","is-referenced-by-count":7,"title":["A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory"],"prefix":"10.1109","author":[{"given":"Qian","family":"Zhao","sequence":"first","affiliation":[]},{"given":"Kyosei","family":"Yanagida","sequence":"additional","affiliation":[]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[]},{"given":"Morihiro","family":"Kuga","sequence":"additional","affiliation":[]},{"given":"Toshinori","family":"Sueyoshi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606687"},{"key":"14","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TVLSI.2004.824300","article-title":"The effect of LUT and cluster size on deep- submicron FPGA performance and density","volume":"12","author":"ahmed","year":"2004","journal-title":"IEEE Trans on Very Large Scale Integration (VLSI) Systems"},{"key":"11","first-page":"354","article-title":"Combinational and sequential mapping with priority cuts","author":"mishchenko","year":"2007","journal-title":"Proc of the International Conference on Computer-aided design(ICCAD2007)"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722215"},{"journal-title":"Stratix II architecture","year":"2005","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2153883"},{"key":"7","article-title":"IWLS'93 benchmark set: Version 4.0","author":"mcelvain","year":"1993","journal-title":"Distributed as part of the MCNC International Workshop on Logic Synthesis '93 benchmark distribution"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243959"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E95.D.294"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/12.713316"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893581"},{"year":"0","author":"bets","key":"8"}],"event":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2014,9,2]]},"location":"Munich, Germany","end":{"date-parts":[[2014,9,4]]}},"container-title":["2014 24th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6913605\/6927322\/06927460.pdf?arnumber=6927460","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T18:53:19Z","timestamp":1498157599000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6927460\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fpl.2014.6927460","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}