{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:49:41Z","timestamp":1729651781565,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/fpl.2014.6927466","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T17:13:21Z","timestamp":1413998001000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Pipelined reconfigurable multiplication with constants on FPGAs"],"prefix":"10.1109","author":[{"given":"Konrad","family":"Moller","sequence":"first","affiliation":[]},{"given":"Martin","family":"Kumm","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Kleinlein","sequence":"additional","affiliation":[]},{"given":"Peter","family":"Zipf","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Structures and Methods for Implementing Ternary Adders\/Subtractors in Programmable Logic Devices","year":"2006","author":"simkins","key":"17"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645543"},{"journal-title":"Logic Cell Supporting Addition of Three Binary Words","year":"2009","author":"baeckler","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2010.5757741"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.44"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.893549"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030446"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1009780"},{"key":"2","first-page":"11\/1","article-title":"multiplication by an integer using minimum adders","author":"dempster","year":"1994","journal-title":"IEE Colloquium on Mathematical Aspects of Digital Signal Processing (Digest No 1994\/034)"},{"key":"1","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1049\/ip-g-2.1991.0066","article-title":"primitive operator digital filters","volume":"138","author":"bull","year":"1991","journal-title":"Circuits Devices and Systems IEE Proceedings G"},{"key":"10","first-page":"159","article-title":"Dynamically reconfigurable constant multiplication on FPGAs","author":"m\ufffdller","year":"2014","journal-title":"11 Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'08)"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6272072"},{"year":"2014","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1240233.1240234"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837424"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-007-9005-8"},{"year":"2014","key":"8"}],"event":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2014,9,2]]},"location":"Munich, Germany","end":{"date-parts":[[2014,9,4]]}},"container-title":["2014 24th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6913605\/6927322\/06927466.pdf?arnumber=6927466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T18:53:17Z","timestamp":1498157597000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6927466\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/fpl.2014.6927466","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}