{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:03:17Z","timestamp":1729630997758,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/fpl.2014.6927492","type":"proceedings-article","created":{"date-parts":[[2014,10,22]],"date-time":"2014-10-22T17:13:21Z","timestamp":1413998001000},"page":"1-6","source":"Crossref","is-referenced-by-count":10,"title":["PR-HMPSoC: A versatile partially reconfigurable heterogeneous Multiprocessor System-on-Chip for dynamic FPGA-based embedded systems"],"prefix":"10.1109","author":[{"given":"Tuan D. A.","family":"Nguyen","sequence":"first","affiliation":[]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272463"},{"journal-title":"Xilinx Partial Reconfiguration User Guide","year":"2013","key":"17"},{"journal-title":"Xilinx Data2MEM User Guide","year":"2009","key":"18"},{"journal-title":"LogiCORE IP XPS Timer\/Counter (V1 02a)","year":"2010","key":"15"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681443"},{"journal-title":"Xilinx MicroBlaze Debug Module (MDM)","year":"2012","key":"13"},{"journal-title":"Logicore Ip Multi-port Memory Controller (Mpmc)","year":"2011","key":"14"},{"journal-title":"LogiCORE IP XPS HWICAP(v5 00a)","year":"2010","key":"11"},{"journal-title":"XPS SYSACE (System ACE) Interface Controller","year":"2009","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2009.37"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1109\/IPDPS.2011.139","article-title":"High speed partial runtime reconfiguration using enhanced ICAP hard macro","author":"hansen","year":"2011","journal-title":"Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1367045.1367049"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78610-8_34"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2138140"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/121353"},{"key":"5","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1109\/DDECS.2013.6549812","article-title":"Relocation of reconfigurable modules on Xilinx FPGA","author":"drahonovsky","year":"2013","journal-title":"Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2013 IEEE 16th International Symposium on"},{"key":"4","article-title":"Partial reconfiguration on FPGAs: Architectures","volume":"153","author":"koch","year":"2012","journal-title":"Tools and Applications"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.176"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.93"}],"event":{"name":"2014 24th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2014,9,2]]},"location":"Munich, Germany","end":{"date-parts":[[2014,9,4]]}},"container-title":["2014 24th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6913605\/6927322\/06927492.pdf?arnumber=6927492","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T18:53:19Z","timestamp":1498157599000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6927492\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/fpl.2014.6927492","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}