{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:05:05Z","timestamp":1767261905574},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7293940","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T21:58:09Z","timestamp":1444341489000},"page":"1-8","source":"Crossref","is-referenced-by-count":11,"title":["From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis"],"prefix":"10.1109","author":[{"given":"Joao","family":"Andrade","sequence":"first","affiliation":[]},{"given":"Nithin","family":"George","sequence":"additional","affiliation":[]},{"given":"Kimon","family":"Karras","sequence":"additional","affiliation":[]},{"given":"David","family":"Novo","sequence":"additional","affiliation":[]},{"given":"Vitor","family":"Silva","sequence":"additional","affiliation":[]},{"given":"Paolo","family":"Ienne","sequence":"additional","affiliation":[]},{"given":"Gabriel","family":"Falcao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CCNC.2013.6488484"},{"key":"ref11","first-page":"273","article-title":"FPGA Implementations of LDPC over GF(2m) Decoders","author":"spagnol","year":"2007","journal-title":"Proc IEEE SiPS"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2279186"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071830"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISTC.2010.5613874"},{"year":"0","key":"ref15","article-title":"Accelerating OpenCV Applications with Zynq-7000 All Programmable SoC using Vivado HLS Video Libraries"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2003.1222728"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"year":"0","key":"ref6","article-title":"The Xilinx SDAccel Development Environment"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1002\/9780470740415"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6853936"},{"journal-title":"Programming Massively Parallel Processors A Hands-on Approach","year":"2012","author":"kirk","key":"ref7"},{"key":"ref2","first-page":"13","article-title":"A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services","author":"putnman","year":"2014","journal-title":"Proc ACM\/IEEE ISCA"},{"key":"ref1","article-title":"Google's project ARA smartphones to use lattice ECP5 FPGAs","author":"maxfield","year":"2014","journal-title":"EE Times"},{"key":"ref9","first-page":"45","article-title":"Implementation of an LDPC decoder for IEEE 802.11n using Vivado High-Level Synthesis","author":"scheiber","year":"2013","journal-title":"Proc IEEE ICECS"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07293940.pdf?arnumber=7293940","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T22:42:34Z","timestamp":1490395354000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7293940\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7293940","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}