{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:52:42Z","timestamp":1780674762855,"version":"3.54.1"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7293953","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T21:58:09Z","timestamp":1444341489000},"page":"1-6","source":"Crossref","is-referenced-by-count":12,"title":["An efficient reconfigurable architecture by characterizing most frequent logic functions"],"prefix":"10.1109","author":[{"given":"Iman","family":"Ahmadpour","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Behnam","family":"Khaleghi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hossein","family":"Asadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Generating efficient libraries for use in FPGA resynthesis algorithms. Department of Electrical and Computer Engineering, University of Waterloo","author":"kennings","year":"2010"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243959"},{"key":"ref12","article-title":"Abc: A system for sequential synthesis and verification","author":"mishchenko","year":"2007","journal-title":"url"},{"key":"ref13","year":"2013","journal-title":"Predictive Technology Model (PTM)"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360299"},{"key":"ref16","article-title":"Virtex-6 fpgas configurable logic block","year":"2012","journal-title":"Xilinx TMRTool User Guide"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927504"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.68"},{"key":"ref6","article-title":"Virtex-II platform FPGAs: Complete data sheet","year":"2007","journal-title":"Xilinx Data Sheet"},{"key":"ref5","first-page":"173","article-title":"An efficient hybrid lut\/sop reconfigurable architecture","author":"hsu","year":"2010","journal-title":"International Symposium on VLSI Design Automation and Test (VLSI-DAT) 2010"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722215"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344698"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0739-4"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145715"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","location":"London, United Kingdom","start":{"date-parts":[[2015,9,2]]},"end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07293953.pdf?arnumber=7293953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T22:20:30Z","timestamp":1490394030000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7293953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7293953","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}