{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T00:20:15Z","timestamp":1725754815497},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7293955","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T21:58:09Z","timestamp":1444341489000},"page":"1-8","source":"Crossref","is-referenced-by-count":5,"title":["Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow"],"prefix":"10.1109","author":[{"family":"Jin Hee Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jason H.","family":"Anderson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568636"},{"key":"ref11","article-title":"Asoft++” eFPGA physical design approach with case studies in 180nm and 90nm","author":"aken'ova","year":"2006","journal-title":"IEEE ISVLSI"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/503048.503073"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1007\/3-540-61730-2_13","article-title":"RaPiD Reconfigurable pipelined datapath","author":"ebeling","year":"1996","journal-title":"Field-Programmable Logic Smart Applications New Paradigms and Compilers"},{"key":"ref14","first-page":"3","article-title":"Architectures and algorithms for synthesizable embedded programmable logic cores","author":"kafafi","year":"2003","journal-title":"FPGA"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216924"},{"key":"ref16","first-page":"213","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"FPL"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645503"},{"article-title":"Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays","year":"2014","author":"luu","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348311"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391500"},{"journal-title":"Altera Corp Tech rep","article-title":"Stratix III ALM Logic Structure's 8-Input Fracturable LUT","year":"2015","key":"ref5"},{"article-title":"Archipelago - An Open Source FPGA with Toolflow Support","year":"2014","author":"liu","key":"ref8"},{"key":"ref7","first-page":"665","article-title":"Efficient modeling and floorplanning of embedded-FPGA fabric","year":"2007","journal-title":"FPL IEEE"},{"key":"ref2","first-page":"96","article-title":"Power8: A 12-core server-class processor in 22nm SOI with 7.6tb\/s off-chip bandwidth","author":"fluhr","year":"2014","journal-title":"ISSCC IEEE"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"article-title":"Bridging the gap between soft and hard eFPGA design","year":"2005","author":"aken'ova","key":"ref9"},{"key":"ref20","article-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3.0","author":"yang","year":"1991","journal-title":"Rep Microelectronics Center of North Carolina"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07293955.pdf?arnumber=7293955","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T21:00:23Z","timestamp":1498251623000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7293955\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7293955","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}