{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T01:47:44Z","timestamp":1729648064987,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/fpl.2015.7293979","type":"proceedings-article","created":{"date-parts":[[2015,10,8]],"date-time":"2015-10-08T17:58:09Z","timestamp":1444327089000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs"],"prefix":"10.1109","author":[{"family":"He Qi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oluseyi","family":"Ayorinde","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yu Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benton","family":"Calhoun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"145","DOI":"10.1007\/978-3-540-30117-2_17","article-title":"A dual-Vdd low power FPGA architecture","author":"gayasen","year":"2004","journal-title":"Proc Intl Conf Field Programmable Logic and Appl"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017443"},{"journal-title":"Stratix IV Device Handbook","year":"0","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393249"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"ref5","first-page":"715","article-title":"Low leakage circuit design for FPGAs","author":"luca","year":"2004","journal-title":"Custom Integrated Circuits Conference 2004 Proceedings of the IEEE 2004"},{"key":"ref8","first-page":"213","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"vaughn","year":"1997","journal-title":"Field-Programmable Logic and Applications"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617466"},{"key":"ref2","article-title":"Architecture and CAD for deep-submicron FPGAs","volume":"497","author":"vaughn","year":"2012"},{"key":"ref9","article-title":"Logic Synthesis and Optimization Benchmarks, Version 3.0","author":"yang","year":"1991","journal-title":"Rep Microelectronics Center of North Carolina"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"}],"event":{"name":"2015 25th International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2015,9,2]]},"location":"London, United Kingdom","end":{"date-parts":[[2015,9,4]]}},"container-title":["2015 25th International Conference on Field Programmable Logic and Applications (FPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7284611\/7293744\/07293979.pdf?arnumber=7293979","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T17:00:23Z","timestamp":1498237223000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7293979\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/fpl.2015.7293979","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}